Advanced Clock Drivers Devices

Freescale Semiconductor

11

MPC9894

The following tables summarize the bit configurations for

is then followed by the address of the register that is to be

accessed. In the case of a write, the register address byte is

followed by the data to be written to that register. In the case

of a read, the device will then respond with the data from that

command is issued by the Master to terminate the transfer.

interface.

Boot Mode

via the MBOOT pin, the entire set of writable configuration

registers are written with a 6-byte sequence. This sequence

starts with the Output Configuration Register, and is followed

by the Mode Configuration and Alarm Reset Register, the

Device Configuration and Output Clock Enable Register, the

Input and Feedback Divider Configuration Register, the

Output Power-Up Register and the Feedback Power-Up

Register. This equates to the register sequence of 1, 2, 3, 4,

6, 7. This sequence starts with the start command, the device

select and read/write(write) byte, followed by the beginning

byte address for reading from the EEPROM. This is then

followed by the start command, device select and read/write

(read) and four current address read bytes. The device

EEPROMs such as STMicroelectronics M24C01, or

equivalent.

Slave Address Register

addressed to this device. The seven-bit address is

determined with the fixed value of binary 1101 followed by

variable bits that are obtained from the three address pins.

The three input pins allow for 8 different addresses for a given

clock generator, allowing up to 8 clock generators to be

Address

Register

0x00

Table 11. Slave Address (Register 0 — Read Only)

0x01

Table 12. Output Configuration Register (Register 1 — Read/Write)

0x02

Table 14. Mode Configuration and Alarm Reset Register (Register 2 — Read/Write)

0x03

Table 17. Device Configuration and Output Clock Enable Register (Register 3 — Read/Write)

0x04

Table 22. Input and Feedback Divider Configuration Register (Register 4 — Read/Write)

0x05

Table 24. Status Register (Register 5 — Read Only)

0x06

Table 25. Output Power-Up Register (Register 6 — Read/Write)

0x07

Table 27. Feedback Power-Up Register (Register 7 — Read/Write)

Start

Write

Start

Read

Stop

ACK

ACK

ACK

NoACK

Dev Selection

Dev Selection

Data Out

Byte Addr

Figure 4. Boot Mode Random Access Read

Table 11. Slave Address (Register 0 — Read Only)

Bit

76543

210

Description

not used

ADDR_6

ADD_R5

ADDR_4

ADDR_3

ADDR_2

read from

ADDR[2] pin

ADDR_1

read from

ADR[1] pin

ADDR_0

read from

ADDR[0] pin

Reset default

1101

Preset default

1101