MPC9894

Rev 3, 1/2005

Freescale Semiconductor

Technical Data

© Freescale Semiconductor, Inc., 2005. All rights reserved.

Quad Input Redundant IDCS Clock

Generator

The MPC9894 is a differential input and output, PLL-based Intelligent

Dynamic Clock Switch (IDCS) and clock generator specifically designed for

redundant clock distribution systems. The device receives up to four LVPECL

clock signals and generates eight phase-aligned output clocks. The MPC9894 is

able to detect failing clock signals and to dynamically switch to a redundant clock

signal. The switch from the failing clock to the redundant clock occurs without

interruption of the output clock signal (output clock slews to alignment). The

phase bump typically caused by a clock failure is eliminated. The device offers

eight low-skew clock outputs organized into four output banks, each configurable

to support the different clock frequencies. The extended temperature range of

the MPC9894 supports telecommunication and networking requirements.

Features

•

8 differential LVPECL output pairs

•

Quad-redundancy reference clock inputs

•

IDCS-on-chip intelligent dynamic clock switch

•

Smooth output phase transition during clock failover switch/*

•

Automatically detects clock failures

•

Clock activity monitor

•

Clock qualifier inputs

•

Manual clock select and automatic switch modes

•

21.25 – 340 MHz output frequency range

•

Specified frequency and phase slew rate on clock switch

•

LVCMOS compatible control inputs and outputs

•

External feedback enables zero-delay configurations

•

Output enable/disable and static test mode (PLL bypass)

•

•

Low cycle-to-cycle and period jitter

•

IEEE 1149.1 JTAG Interface

•

100-ball MAPBGA package

•

Supports 2.5 V or 3.3 V supplies with 2.5 V and 3.3 V I/O

•

Junction temperature range –40

°C to +110°C

Functional Description

The MPC9894 is a quad differential redundant input clock generator. The device contains logic for clock failure detection and

auto switching for clock redundant applications. The generator uses a fully integrated PLL to generate clock signals from any one

of four redundant clock sources. The PLL multiplies the frequency of the input reference clock by one, two, four, eight or divides

the reference clock by two or four. The frequency-multiplied clock signal drives four banks of two differential outputs. Each bank

zero-delay capability.

The integrated IDCS continuously monitors all four clock inputs and indicates a clock failure for each clock input. When a false

clock signal is detected on the active clock, the MPC9894 switches to a redundant clock input, forcing the PLL to slowly slew to

alignment and not produce any phase bumps at the outputs. The MPC9894 also provides a manual mode that allows for

user-controlled clock switches.

1.

At coincident rising edges.

MPC9894

QUAD INPUT REDUNDANT

IDCS CLOCK GENERATOR

VF SUFFIX

100-LEAD MAPBGA PACKAGE

CASE 1462-01