MPC9894 datasheet(4/28 Pages) ETC

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Advanced Clock Drivers Devices

Freescale Semiconductor

MPC9894

Table 2. Function Table

Control

Default

Control Inputs

PLL_BYPASS

PLL enabled. The input to output frequency

relationship is according to Table 9 if the PLL is

frequency locked.

PLL bypassed and IDCS disabled. The VCO output is

replaced by the reference clock signal fREF. This is

considered to be a test mode and clock monitoring and

clock switching are disabled during this operation.

CLK_VALID[3:0]

The associated clock input is considered to be invalid

and usable

The associated clock input is considered to be a valid

usable clock input

CLK_ALARM_RST

CLK_STAT[3:0] and SEL_STAT[1:0] flags are reset:

CLK_STAT[3:0] = 0000 and SEL_STAT[1:0] = 00.

CLK_ALARM_RST is a one-shot function.

CLK_STAT[3:0] and SEL_STAT[1:0] flags are active

Reset of data generators and output dividers. The

MPC9894 requires reset at power-up and after any

loss of PLL lock. Loss of PLL lock may occur when the

external feedback path is interrupted. The length of the

reset pulse should be greater than two reference clock

cycles

Outputs enabled (active)

MBOOT

I2C read/write mode

I2C boot mode

PRESET

Normal Operation

Uses Configuration Register PRESET values on MR

EX_FB_SEL

Selects internal feedback path

Selects external feedback path

MEDIA

Low output impedance (QA0 to QD1 and QFB)

Ω output impedance (QA0 to QD1 and QFB)

SEL_2P5V

Selects 3.3 V for core VDD

Selects 2.5 V for core VDD

MSTROUT_EN

All outputs disabled (synchronous with clock being low) All outputs enabled

Control Outputs

LOCK(1)

1. The combined pins of LOCK = 1 and BUSY = 0 are used to indicate a catastrophic failure. Refer to PLL Out-of-Lock Conditions.

PLL is locked

PLL is unlocked

BUSY(1)

The IDCS has initiated a clock switch.

No clock switch currently performed

INT

IDCS status has changed (indicates an assertion of

CLK_STAT[3:0] or deassertion of LOCK)

No status change

CLK_STAT[3:0]

Associated clock input not valid

Associated clock input valid

SEL_STAT[1:0]

Encoded value refer to Table 7

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