MPC9894 datasheet(8/28 Pages) ETC

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Advanced Clock Drivers Devices

Freescale Semiconductor

MPC9894

IDCS Manual Mode

The manual request IDCS mode is selected by

IDCS_MODE[2:0] = 0xx. The PLL functions normally and all

four inputs clocks are monitored. The reference clock will

always be the clock signal selected by IDCS_MODE[1:0] and

will be indicated by SEL_STAT[1:0]. A manual-requested

clock switch (by changing the IDCS_MODE[0xx] signal) will

only be executed if the new clock is valid. The SEL_STAT[1:0]

pins/bits should be checked after the manual request to

ensure the clock switch occurred.

Interrupt Operation

The MPC9894 pin, INT, may be used to interrupt a

microprocessor or microcontroller. This open drain output pin

goes active or low on any of the following occurrences

A clock failure as indicated by any of bits 6 thru 3 being

set in the status register

A out-of-lock condition for the PLL as indicated by either

the LOCK pin or bit 2 of the status register.

The interrupted processor would then use the I2C interface

to read the status register (bit 7) to determine if this MPC9894

generated the interrupt. If the interrupt was caused by this

MC9894, the status register would then be analyzed to

determine the reason for the interrupt and then the

appropriate action taken.

In order for interrupts to occur, the INT_E bit must be set in

the Device Configuration and Output Clock Enable Register.

Once the interrupt flag has been set, reading of the Status

Clock Operation on Power-Up

On or after power-up, the MPC9894 must be reset via the

pin. The MPC9894 may be powered-up in either of three

configurations. These configurations are selected by the

PRESET pin and MBOOT pin.

If PRESET is low, on release of the MR pin, the MPC9894

powers up in a benign mode with all clock outputs disabled.

The device is ready to be and must be programmed via the

I2C interface prior to operation.

If the PRESET pin is high on the release of the MR pin, the

MPC9894 powers up in a run state. In this case the IDCS is

configured for automatic mode, CLK0 to be the primary clock,

a divide by 2 on clock bank A and B outputs, a divide by 8 on

clock C and D outputs, all clock output banks enabled and

interrupts enabled. If using the preset mode, then at least one

of the clock inputs must have the correct input frequency prior

to MR going high.

Later in this document, tables defining the I2C interface

registers describe both configurations. The default (reset)

information is for the normal reset operation, while the default

(preset) information describes the values for each

configuration bit on activation of the PRESET pin. In order to

return the MPC9894 to either the preset or reset configuration

the MR pin must be activated.

Refer to the Boot Mode for a description of the MBOOT

pin.

PLL Feedback

The MPC9894 may be operated with either an internal or

an external PLL feedback path. The selection of internal vs.

external feedback is made with the pin, EX_FB_SEL. If

external feedback is desired, the EX_FB_SEL pin should be

connected to VDD and a connection from QFB/QFB to FB_IN/

FB_IN

must be made. External feedback provides a known

relationship between the clock input and the feedback input

for phase synchronization of output clock signals to the clock

input. If this phase synchronization is not required, the

MPC9894 may be configured for internal feedback by the

connection of EX_FB_SEL to ground. In this configuration,

the connection from the feedback output to the feedback

input is not required. The feedback output may be used as a

separate output to produce a reference clock output.

PLL Out-of-Lock Conditions

The LOCK pin and associated status bit indicates the lock

state of the PLL. After power-up and prior to writing

configuration data to the control registers, an out-of-lock

condition will be indicated by LOCK = 1. If a valid clock is

available and proper configuration data is written to the

control registers, LOCK will then indicate the PLL is in a

locked condition with LOCK =0.

The combination of LOCK = 1 and BUSY = 0 is used to

indicate a catastrophic failure of the PLL. This condition will

occur on the following:

All input clocks have failed or no clock is present.

External feedback has been selected with the

EX_FB_SEL pin and an external feedback signal is not

present on the FB_IN/FB_IN inputs. It should be noted

that if this condition occurs during the initial PLL lock

acquisition the PLL will produce a clock that is locked to

the internal feedback path. However, the catastrophic

failure status of LOCK = 1 and BUSY = 0 will occur.

Recovery from the catastrophic failure condition requires

repairing the cause of the failure, followed by a master reset

to be issued to the MPC9894.

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