MP8865

– SYNCHRONOUS STEP-DOWN CONVERTER

MP8865 Rev. 1.03

www.MonolithicPower.com

15

1/18/2018

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Enable/SYNC Control

EN/SYNC is a digital control pin that turns the

Drive EN high to turn on the regulator; drive EN

low to turn off the regulator

. An internal 1MΩ

resistor from EN to GND allows EN/SYNC to be

floated to shut down the chip.

EN is clamped internally using a 6.5V series-

Zener-diode

(see

Fig.

Error!

Reference

source not found.5). Connecting the EN input

through a pull-up resistor to the voltage on VIN

limits the EN input current to less than 100µA.

Connecting EN directly to a voltage source

without a pull-up resistor requires limiting the

amplitude of the voltage source to <6V to

prevent damage to the Zener diode.

Figure 5. 6.5V Zener Diode Connection

The chip can be synchronized to an external

clock range from 300kHz up to 2MHz through

EN (as soon as an external clock is added); the

internal clock rising edge is synchronized to the

external clock rising edge. Select an external

clock signal with a pulse width less than 80% of

one internal clock cycle time.

Under-Voltage Lockout (UVLO)

Under-voltage lockout (UVLO) protects the chip

from operating at an insufficient supply voltage.

The MP8865 UVLO comparator monitors the

output voltage of the internal regulator (VCC).

The UVLO rising threshold is about 4V while its

falling threshold is 3.4V.

Soft-Start (SS)

The

MP8865

employs

a

soft-start

(SS)

mechanism to ensure a smooth output during

power-up. When EN becomes high, an internal

current source (12

μA) charges up the SS

capacitor. The SS capacitor voltage takes over

output voltage smoothly ramps up with the SS

voltage. Once the SS voltage reaches the same

this point, the soft-start is complete and the

device enters steady-state operation.

The SS capacitor value can be determined as

follows:

 

 

 

 



SS

SS

REF

T

ms

I

A

C

nF

VV

If

the

output

capacitors

have

a

large

capacitance value, it is NOT recommended to

set the SS time too small. Otherwise, it will be

easy to hit the current limit during SS.

Pre-Bias Start-Up

The

MP8865

has

been

designed

for

a

monotonic start-up into a pre-biased output

voltage. If the output is pre-biased to a certain

voltage during start-up, the voltage on the soft-

start capacitor will be charged. When the soft-

s

tart capacitor’s voltage exceeds the sensed

high-side

and

low-side

power

switches

sequentially. Output voltage starts to ramp up

following the soft-start slew rate.

Note:

control loop.

Power Good (PG) Indicator

The MP8865 has a power good (PG) output

used to indicate whether the output voltage of

the module is ready. PG is an open-drain

output. Connect PG to VCC (or another voltage

source) through a pull-

up resistor (e.g. 100kΩ).

When the input voltage is applied, PG is pulled

down to GND before the internal SS is ready

80us delay). During normal operation, PG is

When UVLO or OTP occurs, PG is pulled low

immediately; when OC (over current) occurs,

PG will NOT respond to an output over-voltage

condition.

indication as the external PG.