MP8865

– SYNCHRONOUS STEP-DOWN CONVERTER

MP8865 Rev. 1.03

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18

1/18/2018

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consisting of a data line (SDA) and a clock line

(SCL). The lines are pulled externally to a bus

voltage when they are “idle.” Connected to the

line, a master device generates the SCL signal

and

addresses

and

arranges

the

communication

sequence.

The

MP8865

fast mode (400kHz) and high-speed mode

(3.4Mhz), adding flexibility to the power-supply

solution. The output voltage, transition slew

rate, and other parameters can be controlled

Data Validity

One clock pulse is generated for each data bit

transferred. The data on the SDA line must be

stable during the high period of the clock. The

high or low state of the data line can only

change when the clock signal on the SCL line is

low (see Fig. 7).

Start and Stop Conditions

The start and stop conditions are signaled by

the master device, which signifies the beginning

condition

is

defined

as

the

SDA

signal

transitioning from high to low while the SCL is

high. The stop condition is defined as the SDA

signal transitioning from low to high while the

SCL is high (see Fig. 8).

Figure 8. Start and Stop Conditions

Start and Stop conditions are generated always

by the master. The bus is considered

busy after the start condition. The bus is

considered free again after a minimum of 4.7uS

after the stop condition. The bus stays busy if a

repeated start (Sr) is generated instead of a

stop condition. The start (S) and repeated start

(Sr) conditions are functionally identical.

Transfer Data

Every byte put on the SDA line must be 8-bits

long. Each byte must be followed by an

acknowledge

bit.

The

acknowledge-related

clock pulse is generated by the master. The

transmitter releases the SDA line (high) during

the acknowledge clock pulse. The receiver

must pull down the SDA line during the

acknowledge clock pulse, so that it remains

stable low during the high period of the clock

pulse.

Data transfers follow the format shown in Fig. 8.

After the start condition (S), a slave address is

sent. This address is 7-bits long followed by an

eighth bit, which is a data direction bit (R/W). A

‘0’ indicates a transmission (write), and a ‘1’

indicates a request for data (read). A data

transfer

is

terminated

always

by

a

stop

condition (P) generated by the master. However,

if a master still wishes to communicate on the

bus, it can generate a repeated start condition

(Sr) and address another slave without first

generating a stop condition.

Figure 9. A Complete Data Transfer

The MP8865 requires a start condition, a valid

byte for a single data update. After receipt of

each byte, the MP8865 acknowledges by

pulling the SDA line low during the high period

selects the MP8865. The MP8865 performs an

update on the falling edge of the LSB byte.