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MP8865 Datasheet(PDF) 24 Page - Monolithic Power Systems

Part # MP8865
Description  High-Efficiency, 6A, 21V, Synchronous Step-Down Converter with I2C Interface
PDF  29 Pages
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Manufacturer  MPS [Monolithic Power Systems]
Direct Link  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

MP8865 Datasheet(HTML) 24 Page - Monolithic Power Systems

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MP8865
– SYNCHRONOUS STEP-DOWN CONVERTER
MP8865 Rev. 1.03
www.MonolithicPower.com
24
1/18/2018
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
External Bootstrap Diode
An external bootstrap diode enhances the
efficiency of the regulator given the following
conditions:
VOUT is 5V or 3.3V
The duty cycle is high: D=
IN
OUT
V
V
>65%
In these cases, add an external BST diode from
VCC to BST (see Fig. 12).
Figure 12. Optional External Bootstrap Diode to
Enhance Efficiency
The recommended external BST diode is
IN4148, and the BST capacitor value is 0.1µF
to 1μF.
PCB Layout Guidelines(11)
Efficient PCB layout is critical to achieve stable
operation, especially for VCC capacitor and
input capacitor placement. For best results,
refer to Fig. 13 and follow the guidelines below:
1)
Use
a
large
ground
plane
connected
directly to GND. If bottom layer is ground
plane, add vias near GND.
2)
Place as close as possible the VCC
capacitor to VCC and GND. Make the trace
length of VCC to the VCC capacitor anode
to the VCC capacitor cathode chip to GND
as short as possible.
3)
Place the ceramic input capacitor close to
IN and GND. Keep the connection of the
input capacitor and IN as short and wide as
possible.
4)
Route SW and BST away from sensitive
analog areas (such as FB). It is NOT
recommended to route SW and BST traces
under the
chip’s bottom layer.
5)
Place the T-type feedback resistor R3 close
to the chip to ensure the trace (which
connects to FB) is as short as possible.
Notes:
11) The recommended layout is based on Fig. 15
in the “Typical
Application Circuit
s” section on page 26.
Top Layer
Bottom Layer
Figure 13. Recommended PCB Layout



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