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MP8869 Datasheet(PDF) 19 Page - Monolithic Power Systems

Part # MP8869
Description  17V, 12A, High-Efficiency, Synchronous Step-Down Converter with Integrated Telemetry via I2C Interface
PDF  37 Pages
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Manufacturer  MPS [Monolithic Power Systems]
Direct Link  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

MP8869 Datasheet(HTML) 19 Page - Monolithic Power Systems

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MP8869
– 17V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE
MP8869 Rev.1.0
www.MonolithicPower.com
19
6/8/2016
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
Under-Voltage Lockout (UVLO)
Under-voltage lockout (UVLO) protects the chip
from operating at an insufficient supply voltage.
The MP8869 UVLO comparator monitors the
input voltage, VIN, and output voltage of the
VCC regulator. The MP8869 is active when the
voltages exceed the UVLO rising threshold.
Soft-Start (SS) and Pre-Bias Start-Up
The soft start (SS) prevents the converter
output voltage from overshooting during start-
up. When the chip starts up, the internal
circuitry generates a soft-start voltage that
ramps up from 0V to VCC. When SS is lower
than REF, the error amplifier uses SS as the
reference. When SS is higher than REF, the
error amplifier uses REF as the reference.
The approximate typical soft-start time can be
calculated with Equation (2):
( )
(
)
()
7
ref
ss
ss
V
V
C
nF
t
ms
A
(2)
Where Vref is reference voltage of the FB loop or
I
2C loop.
If the output of the MP8869 is pre-biased to a
certain voltage during start-up, the IC disables
the switching of both the HS-FET and LS-FET
until the voltage on the internal SS capacitor
exceeds the sensed output voltage at FB or
VOUT
(7).
NOTE:
7) V_BOOT = 1, sense FB voltage. V_BOOT = 0, sense VOUT
voltage.
The MP8869 also provides a selectable soft-
stop
function
which
defines
the
output
discharge behavior after EN shutdown. By
default, the output is not controlled after EN
shutdown. If setting the soft-stop control bit D[3]
to 1 in register 02 via the I
2C, the output is
discharged linearly to zero in a quarter of the
soft-start time.
Over-Current-Protection (OCP)
The MP8869 has a default, hiccup, cycle-by-
cycle, over-current limiting control. The current-
limit circuit employs both high-side current limit
and
a
low-side
"valley"
current-sensing
algorithm. The MP8869 uses the RDS(ON) of the
LS-FET as a current-sensing element for the
valley current limit. If the magnitude of the high-
side current-sense signal is above the current-
limit threshold, the PWM on pulse is terminated,
and the LS-FET is turned on. Afterward, the
inductor current is monitored by the voltage
between GND and SW. GND is used as the
positive current sensing node, so GND should
be connected to the source terminal of the
bottom MOSFET. PWM is not allowed to initiate
a new cycle before the inductor current falls to
the valley threshold.
After
the
cycle-by-cycle
over-current
limit
occurs, the output voltage drops until VOUT is
below
the
under-voltage
(UV)
threshold,
typically 60% below the reference. Once UV is
triggered, the MP8869 enters hiccup mode to
restart the part periodically. This protection
mode is especially useful when the output is
dead shorted to ground. The average short-
circuit current is greatly reduced to alleviate
thermal issues and protect the regulator. The
MP8869 exits hiccup mode once the over-
current condition is removed.
Short the output to ground first, and then power
on the part. The MP8869
’s I2C is disabled in
this condition. The I
2C resumes operation after
the short circuit is removed. When hiccup OCP
bit D[1] in register 01 is set to 0 by the I
2C, a
latch-off occurs if OCP is triggered, and FB
UVP is triggered.
Power Good (PG)
The power good (PG) indicates whether the
output voltage is in the normal range compared
to the internal reference voltage. PG is an
open-drain structure. An external pull-up supply
is required. During power-up, the PG output is
pulled low. This indicates to the system to
remain off and keep the load on the output to a
minimum. This helps reduce in-rush current at
start-up.
When the output voltage is higher than 90%
and lower than 115% of the internal reference
voltage, and the soft start is finished, then the
PG signal is pulled high. When the output
voltage is lower than 85% after the soft start
finishes, the PG signal remains low. When the
output voltage is higher than 115% of the
internal reference, PG is switched low. The PG
signal rises high again the after output voltage
drops below 105% of the internal reference
voltage.



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