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MP8869 Datasheet(PDF) 8 Page - Monolithic Power Systems

Part # MP8869
Description  17V, 12A, High-Efficiency, Synchronous Step-Down Converter with Integrated Telemetry via I2C Interface
PDF  37 Pages
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Manufacturer  MPS [Monolithic Power Systems]
Direct Link  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

MP8869 Datasheet(HTML) 8 Page - Monolithic Power Systems

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MP8869
– 17V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
MP8869 Rev.1.0
www.MonolithicPower.com
8
6/8/2016
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
I
2C PORT SIGNAL CHARACTERISTICS
Parameter
Symbol
Condition
Cb = 100pF
Cb = 400pF
Units
Min
Max
Min
Max
SCLH and SCL clock
frequency
fSCHL
0
3.4
0
0.4
MHz
Set-up time for a
repeated start condition
τ
SU;STA
160
-
600
-
ns
Hold-time (repeated)
start condition
τ
HD;STA
160
-
600
-
ns
Low period of the SCL
clock
τ
LOW
160
-
1300
-
ns
High period of the SCL
clock
tHIGH
60
-
600
-
ns
Data set-up time
τ
SU:DAT
10
-
100
-
ns
Data hold time
τ
HD;DAT
0
70
0
-
ns
Rise time of SCLH signal
τ
rCL
10
40
20*0.1Cb
300
ns
Rise time of SCLH signal
after a repeated start
condition and after an
acknowledge bit
τ
fCL1
10
80
20*0.1Cb
300
ns
Fall time of SCLH signal
τ
fCL
10
40
20*0.1Cb
300
ns
Rise time of SDAH signal
τ
fDA
10
80
20*0.1Cb
300
ns
Fall time of SDAH signal
τ
fDA
10
80
20*0.1Cb
300
ns
Set-up time for stop
condition
τ
SU;STO
160
-
600
-
ns
Bus free time between a
stop and start condition
τ
BUF
160
-
1300
-
ns
Data valid time
τ
VD;DAT
-
16
-
90
ns
Data valid acknowledge
time
τ
VD;ACK
-
160
-
900
ns
Capacitive load for each
bus line
Cb
SDAH and SCLH line
-
100
-
400
pF
SDAH + SDA line and
SCLH + SCL line
-
400
-
400
pF
Noise margin at the low
level
Ci
For each connected
device
-
0.1VCC
0.1VCC
-
V
Noise margin at the high
level
VnH
For each connected
device
-
0.2VCC
0.2VCC
-
V
NOTE:
VCC is the I
2C bus voltage, 3.0V to 3.6V range, 3.3V typical.



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