MP8869 datasheet(22/37 Pages) MPS

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MP8869

– 17V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER

PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE

MP8869 Rev.1.0

www.MonolithicPower.com

6/8/2016

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

2C INTERFACE

2C Serial Interface Description

The I

2C is a 2-wire, bidirectional, serial interface

consisting of a data line (SDA) and a clock line

(SCL). The lines are pulled to a bus voltage

externally when they are idle. When connecting

to the line, a master device generates an SCL

signal and device address and arranges the

communication

sequence.

The

MP8869

interface is an I

2C slave. The I2C interface adds

flexibility to the power supply solution. The

output voltage, transition slew rate, and other

parameters can be controlled by the I

interface instantaneously.

Data Validity

One clock pulse is generated for each data bit

transferred. The data on the SDA line must be

stable during the high period of the clock. The

high or low state of the data line can only

change when the clock signal on the SCL line is

low (see Figure 7).

Figure 7: Bit Transfer on the I

2C Bus

Start and stop are signaled by the master

device, which signifies the beginning and the

end of the I

2C transfer. The start condition is

defined as the SDA signal transitioning from

high to low while the SCL is high. The stop

condition

defined

the

SDA

signal

transitioning from low to high while the SCL is

high (see Figure 8).

Figure 8: Start and Stop Conditions

Start and stop conditions are always generated

by the master. The bus is considered to be

busy after the start condition, and is considered

to be free again after a minimum of 4.7

μs after

the stop condition. The bus remains busy if a

repeated start (Sr) is generated instead of a

stop condition. The start (S) and repeated start

(Sr) conditions are functionally identical.

Transfer Data

Every byte put on the SDA line must be eight

bits long. Each byte must be followed by an

acknowledge

bit.

The

acknowledge-related

clock pulse is generated by the master. The

transmitter releases the SDA line (high) during

the acknowledge clock pulse. The receiver

must pull down the SDA line during the

acknowledge clock pulse so that it remains

stable low during the high period of this clock

pulse.

Data transfers follow the format shown in Figure

9. After the start condition (S), a slave address

is sent. This address is 7 bits long followed by

an eighth data direction bit (R/W). A zero

indicates a transmission (write), and a one

indicates a request for data (read). A data

transfer

always

terminated

stop

condition (P) generated by the master. However,

if a master still wishes to communicate on the

bus, it can generate a repeated start condition

(Sr) and address another slave without first

generating a stop condition.

Figure 9: Complete Data Transfer

The MP8869 requires a start condition, a valid

2C address, a register address byte, and a data

byte for a single data update. After receiving

each byte, the MP8869 acknowledges by

pulling the SDA line low during the high period

of a single clock pulse. A valid I

2C address

selects the MP8869. The MP8869 performs an

update on the falling edge of the LSB byte.

MP8869 Datasheet(PDF) 22 Page - Monolithic Power Systems

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