MP3429

– 21A, HIGH-EFFICIENCY, FULLY INTEGRATED, SYNC, BOOST CONVERTER

MP3429 Rev. 1.0

www.MonolithicPower.com

16

6/8/2017

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

© 2017 MPS. All Rights Reserved.

it forces the LS-FET on. This limits the

frequency, avoiding audible frequency in light-

load or no-load condition.

USM may convert more energy to the output

than the required load due to the minimum

23kHz frequency, which causes VOUT to rise

above the normal voltage setting. When VOUT

internal clamped level, the HS-FET zero-current

detection (ZCD) threshold is regulated to one

negative level gradually, so the energy in the

inductor can flow back to VIN in each cycle. This

keeps the output at the setting voltage with a

>23kHz frequency. The MP3429 also works with

USM has the same efficiency as in PSM if the

frequency is higher than the typical 33kHz. USM

has more power loss than PSM if the frequency

is clamped at the typical 33kHz, but USM does

not introduce audible noise caused by the group

pulse in PSM.

Minimum On Time and Minimum Off Time

The MP3429 blanks the LS-FET on state with

80ns in each cycle to enhance noise immunity.

This 80ns minimum on time restricts applications

with a high VIN/VOUT ratio. The MP3429 also

blanks the LS-FET off state with a minimum off

time in each cycle. During the minimum off time,

the LS-FET cannot turn on, and the minimum off

time is short enough to convert the 0.8V input to

16V.

LS-FET and HS-FET Maximum On Time

an on time of 7.5µs, the MP3429 shuts down the

LS-FET. After the LS-FET is shut down, the

inductor current goes through the HS-FET and

charges VOUT in the off-time period. This helps

refresh VOUT with a minimum frequency of

about 133kHz in heavy-load transient conditions.

During CCM condition, the HS-FET on time is

limited below 8µs. This helps limit the maximum

LS-FET off time when VOUT is close to VIN in

USM. In USM or heavy-load PSM, if VIN is too

close to VOUT, the HS-FET may be turned off by

the 8µs HS-FET maximum on time because the

inductor current cannot ramp down within this

8µs limit. After the HS-FET turns off, the LS-FET

turns on immediately with one pulse control by

makes the LS-FET work in a quasi-constant

minimum duty cycle. If VIN is high enough,

VOUT is higher than the setting voltage with this

duty cycle ratio. In PSM and light load, the IC

works with normal PSM logic. The IC stops

working when VOUT is higher than the setting

below the setting voltage.

VDD Power

The MP3429 internal circuit is powered by VDD.

A ceramic capacitor no less than 4.7

μF is

required on VDD. When VIN is lower than 3.4V,

VDD is powered from the higher value of either

VIN or VOUT. This allows the MP3429 to

with a low input voltage. When VIN is higher than

3.4V, VDD is always powered by VIN. This

decreases the VOUT to VDD regulator loss,

because VOUT is always higher than VIN.

If VDD is powered by an external supply, and the

voltage is higher than 3.4V, the regulators from

VIN and VOUT are disabled. In this condition,

the MP3429 starts once the external VDD power

low as 0.9V. When VDD is powered by the

external power supply, the MP3429 continues

working, even if both VIN and VOUT are

dropping but are higher than 0.8V. The external

VDD power source should be limited within 3.6V.

There is a reverse-blocking circuit to limit the

current flowing between VIN and VOUT. If the

external VDD power is higher than the VDD

regulation voltage, the current is supplied from

the external power, and there is no path for the

current from VDD to VIN or from VDD to VOUT.

VDD is charged when VIN is higher than about

0.9V and EN is higher than the micro-power

threshold. If EN is low, VDD is disconnected from

VIN and VOUT. Supply VIN with a power source

higher than 2.7V during VIN start-up to provide

enough VDD power voltage.