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MP2953B Datasheet(PDF) 16 Page - Monolithic Power Systems |
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MP2953B Datasheet(HTML) 16 Page - Monolithic Power Systems |
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16 / 30 page ![]() MP2953B – DIGITAL PWM CONTROLLER WITH PMBUS FOR VR12.5 MP2953B Rev. 1.01 www.MonolithicPower.com 16 10/9/2015 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. FIGURE 4(a). Steady State with Load @160A Load transient performance is illustrated in Figures 4(b)—(d). The MP2953B adaptively changes the switching frequency of each individual phase during load transient to achieve fast closed-loop speed. Only one set of loop compensation is needed, so it is very easy to set the loop parameter. Fig. 4(b) shows no ring-back when the load steps up from 36A to 180A. Fig. 4(c) shows that the overshoot of the output voltage is small during load release. Fig. 4(d) shows the high-load transient rate; the output voltage is stable. The MP2953B meets Intel VR12.5 standards with a minimum number of output capacitors. FIGURE 4(b). Load Step Up @ 1kHz FIGURE 4(c). Load Step Down @ 1kHz FIGURE 4(d). Load Step @1MHz Power State Change The SVID bus changes the VR into different power states to achieve high efficiency during light-load conditions. These states are entered by programming the power-state register using SVID’s SetPS command. The VR optimizes its power loss to flatten the efficiency curve over the operating current range with the power-state commands issued by the CPU. In PS0 mode, all phases run in CCM. In PS1 mode (<20A load, typically), only one phase runs with synchronous switching; the other phases are in tri-state. In PS2 mode (<5A load, typically), only one phase runs in the diode emulation mode; the switching frequency decreases automatically due to the light-load condition. |
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