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LTC3121 Datasheet(PDF) 7 Page - Linear Technology |
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LTC3121 Datasheet(HTML) 7 Page - Linear Technology |
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7 / 26 page ![]() LTC3121 7 3121fa For more information www.linear.com/LTC3121 pin FuncTions SW (Pin 1): Switch Pin. Connect an inductor from this pin to VIN. Keep PCB trace lengths as short and wide as possible to reduce EMI and voltage overshoot. When VOUT ≥ VIN + 2V, an internal anti-ringing resistor is connected betweenSWandVINaftertheinductorcurrenthasdropped to near zero, to minimize EMI. The anti-ringing resistor is also activated in shutdown and during the sleep periods of Burst Mode operation. PGND (Pin 2, Exposed Pad Pin 13): Power Ground. When laying out your PCB, provide a short, direct path between PGNDandthe outputcapacitorandtiedirectlytotheground plane. The exposed pad is ground and must be soldered to the PCB ground plane for rated thermal performance. VIN (Pin 3): Input Supply Pin. The device is powered from VIN unless VOUT exceeds VIN and VIN is less than 3V. Place a low ESR ceramic bypass capacitor of at least 4.7µF from VIN to PGND. X5R and X7R dielectrics are preferred for their superior voltage and temperature characteristics. PWM/SYNC (Pin 4): Burst Mode Operation Select and Oscillator Synchronization. Do not leave this pin floating. • PWM/SYNC = High. Disable Burst Mode Operation and maintain low noise, constant frequency operation. • PWM/SYNC = Low. The converter operates in Burst Mode operation, independent of load current. • PWM/SYNC = External CLK. The internal oscillator is synchronized to the external CLK signal. Burst Mode operation is disabled. A clock pulse width between 100ns and 2µs is required to synchronize the oscillator. An external resistor must be connected between RT and GND to program the oscillator slightly below the desired synchronization frequency. In non-synchronized applications, repeated clocking of the PWM/SYNC pin to affect an operating mode change is supported with these restrictions: • Boost Mode (VOUT > VIN): IOUT <500µA: ƒPWM/SYNC ≤ 100Hz, IOUT ≥ 500µA: ƒPWM/SYNC ≤ 5kHz • Buck Mode (VOUT < VIN): IOUT <5mA: ƒPWM/SYNC ≤ 5Hz, IOUT ≥ 5mA: ƒPWM/SYNC ≤ 5kHz VCC (Pin 5): VCC Regulator Output. Connect a low-ESR filter capacitor of at least 4.7µF from this pin to GND to provide an internal regulated rail approximately equal to the lower of VIN and 4.25V. When VOUT is higher than VIN, and VIN falls below 3V, VCC will regulate to the lower of approximately VOUTand4.25V.AUVLOeventoccursifVCC drops below 1.6V. Switching is inhibited, and a soft-start is initiated when VCC returns above 1.7V. RT (Pin 6): Frequency Adjust Pin. Connect an external resistor (RT) from this pin to SGND to program the oscil- lator frequency according to the formula: RT = 57.6/ƒOSC where ƒOSC is in MHz and RT is in kΩ. VC (Pin 7): Error Amplifier Output. A frequency compen- sation network is connected to this pin to compensate the control loop. See Compensating the Feedback Loop section for guidelines. FB (Pin 8): Feedback Input to the Error Amplifier. Connect the resistor divider tap to this pin. Connect the top of the divider to VOUT and the bottom of the divider to SGND. The output voltage can be adjusted from 2.2V to 15V ac- cording to this formula: VOUT = 1.202V • (1 + R1/R2) SD(Pin9):LogicControlledShutdownInput.Bringingthis pin above 1.6V enables normal, free-running operation, forcing this pin below 0.25V shuts the LTC3121 down, with quiescentcurrentbelow1μA.Donotleavethispinfloating. SGND (Pin 10): Signal Ground. When laying out a PC board, provide a short, direct path between SGND and the (–) side of the output capacitor. VOUT (Pin 11): Output Voltage Sense and the Source of the Internal Synchronous Rectifier MOSFET. Driver bias is derived from VOUT. Connect the output filter capacitor from VOUT to PGND, as close to the IC as possible. A minimum value of 10µF ceramic is recommended. VOUT is disconnected from VIN when SD is low. CAP (Pin 12): Serves as the Low Reference for the Syn- chronous Rectifier Gate Drive. Connect a low ESR filter capacitor (typically 100nF) from this pin to VOUTtoprovide an elevated ground rail, approximately 5.6V below VOUT, used to drive the synchronous rectifier. |
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