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LTC3121

3121fa

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The current mode zero (Z3) is a right half plane zero

which can be an issue in feedback control design, but is

manageable with proper external component selection.

As a general rule, the frequency at which the open-loop

gain of the converter is reduced to unity, known as the

crossover frequency ƒC, should be set to less than one

third of the right half plane zero (Z3), and under one eighth

of the switching frequency ƒOSC. Once ƒC is selected, the

valuesforthecompensationcomponentscanbecalculated

using a bode plot of the power stage or two generally valid

assumptions: P1 dominates the gain of the power stage

for frequencies lower than ƒC and ƒC is much higher than

P2. First calculate the power stage gain at ƒC, GƒC in V/V.

AssumingtheoutputpoleP1dominatesGƒCforthisrange,

it is expressed by:

GƒC ≈

GDC

ƒC

⎛

⎝

⎜

⎞

⎠

⎟

V/V

Decide how much phase margin (Φm) is desired. Greater

phasemargincanoffermorestabilitywhilelowerphasemar-

gin can yield faster transient response. Typically, Φm≈60°

is optimal for minimizing transient response time while

allowing sufficient margin to account for component vari-

ability. Φ1 is the phase boost of Z1, P2, and P5 while Φ2 is

the phase boost of Z4 and P4. Select Φ1 and Φ2 such that

Φ1 ≤ 74°; Φ2 ≤ 2 • tan

−1

VOUT

1.2V

⎛

⎝

⎜

⎞

⎠

⎟− 90° and

Φ1+ Φ2 = Φm +tan

−1 ƒ

⎛

⎝

⎜

⎞

⎠

⎟

where VOUT is in V and ƒC and Z3 are in kHz.

Setting Z1, P5, Z4, and P4 such that

Z1=

ƒC

, P5 = ƒC a1, Z4 =

ƒC

, P4 = ƒC a2

allows a1 and a2 to be determined using Φ1 and Φ2

a1 = tan2

Φ1+ 90°

⎛

⎝

⎜

⎞

⎠

⎟, a2 = tan

2 Φ2 +90°

⎛

⎝

⎜

⎞

⎠

⎟

The compensation will force the converter gain GBOOST

to unity at ƒC by using the following expression for CC:

CC =

103 • gma •R2 •GƒC a1 − 1

(

) a2

2π • ƒC • R1+R2

(

) a1

(gma in µS, ƒC in kHz, GƒC in V/V)

Once CC is calculated, RC and CF are determined by:

RC =

106 • a1

2π • ƒC •CC

kΩ (ƒC in kHz, CC in pF)

CF =

a1 − 1

The values of the phase lead components are given by

the expressions:

RPL =

R1− a2 •

R1•R2

R1+R2

⎛

⎝

⎜

⎞

⎠

⎟

a2 −1

kΩ and

CPL =

106 a2 −1

(

) R1+R2

(

)

2π • ƒC •R1

2 a2

where R1, R2, and RPL are in kΩ and ƒC is in kHz.

Note that selecting Φ2 = 0° forces a2 = 1, and so the

converter will have Type II compensation and therefore

no feedforward: RPL is open (infinite impedance) and CPL

= 0pF. If a2 = 0.833 • VOUT (its maximum), feedforward is

maximized; RPL = 0 and CPL is maximized for this com-

pensation method.

Once the compensation values have been calculated, ob-

taining a converter bode plot is strongly recommended to

verify calculations and adjust values as required.

Using the circuit in Figure 5 as an example, Table 3 shows

the parameters used to generate the bode plot shown in

Figure 6.

applicaTions inForMaTion

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