LTM4644 datasheet(23/38 Pages) LINER

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LTM4650A

4650afb

For more information www.linear.com/LTM4650A

APPLICATIONS INFORMATION

Figure 10. Graphical Representation of JESD51-12 Thermal Coefficients

Within a SIP (system-in-package) module, be aware there

are multiple power devices and components dissipating

power, with a consequence that the thermal resistances

relative to different junctions of components or die are not

exactly linear with respect to total package power loss. To

reconcile this complication without sacrificing modeling

simplicity—but also, not ignoring practical realities—an

approach has been taken using FEA software modeling

along with laboratory testing in a controlled-environment

chamber to reasonably define and correlate the thermal

resistance values supplied in this data sheet: (1) Initially,

FEA software is used to accurately build the mechanical

geometry of the µModule and the specified PCB with all

of the correct material coefficients along with accurate

power loss source definitions; (2) this model simulates

a software-defined JEDEC environment consistent with

JESD51-9 to predict power loss heat flow and temperature

readingsatdifferentinterfacesthatenablethecalculationof

theJEDEC-definedthermalresistancevalues;(3)themodel

and FEA software is used to evaluate the µModule with

heat sink and airflow; (4) having solved for and analyzed

these thermal resistance values and simulated various

operating conditions in the software model, a thorough

laboratory evaluation replicates the simulated conditions

with thermocouples within a controlled-environment

chamberwhileoperatingthedeviceatthesamepowerloss

as that which was simulated. An outcome of this process

and due-diligence yields a set of derating curves provided

in other sections of this data sheet. After these laboratory

test have been performed and correlated to the µModule

model, then the θJB and θBA are summed together to cor-

relate quite well with the µModule model with no airflow or

heat sinking in a properly define chamber. This θJB + θBA

value is shown in the Pin Configuration section and should

accurately equal the θJA value because approximately

100% of power loss flows from the junction through the

board into ambient with no airflow or top mounted heat

sink. Each system has its own thermal characteristics,

therefore thermal analysis must be performed by the user

in a particular system.

The LTM4650A module has been designed to effectively

remove heat from both the top and bottom of the pack-

age. The bottom substrate material has very low thermal

resistance to the printed circuit board. An external heat

sink can be applied to the top of the device for excellent

heat sinking with airflow.

Figure 11 shows the thermal image of the LTM4650A,

without airflow, without heat sink, running paralleled from

12V to 1V at 50A with around 87.3% efficiency and 7.2W

power loss. Figure 12 shows the thermal image of the

LTM4650A, with 200LFM airflow and external heat sink,

running paralleled form 12V to 5V at 50A with around

95% efficiency and 13W power loss.

4650A F10

µModule DEVICE

JUNCTION-TO-CASE (TOP)

RESISTANCE

JUNCTION-TO-BOARD RESISTANCE

JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)

CASE (TOP)-TO-AMBIENT

RESISTANCE

BOARD-TO-AMBIENT

RESISTANCE

JUNCTION-TO-CASE

(BOTTOM) RESISTANCE

JUNCTION

AMBIENT

CASE (BOTTOM)-TO-BOARD

RESISTANCE

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