LTM4644 datasheet(25/38 Pages) LINER

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LTM4650A

4650afb

For more information www.linear.com/LTM4650A

APPLICATIONS INFORMATION

The derived thermal resistances in Tables 2 and 3 for the

various conditions can be multiplied by the calculated

power loss as a function of ambient temperature to derive

temperature rise above ambient, thus maximum junction

temperature.Roomtemperaturepowerlosscanbederived

from the efficiency curves and adjusted with the above

ambient temperature multiplicative factors. The printed

circuit board is a 1.6mm thick four layer board with two

ounce copper for all four layers. The PCB dimensions are

101mm × 114mm. The BGA heat sinks are listed in Table 3.

Layout Checklist/Example

The high integration of LTM4650A makes the PCB board

layoutverysimpleandeasy.However,tooptimizeitselectri-

cal and thermal performance, some layout considerations

are still necessary.

• Use large PCB copper areas for high current paths,

including VIN, GND, VOUT1 and VOUT2. It helps to

minimize the PCB conduction loss and thermal stress.

• Placehighfrequencyceramicinputandoutputcapaci-

tors next to the VIN, PGND and VOUT pins to minimize

high frequency noise.

• Place a dedicated power ground layer underneath the

unit.

• Tominimizetheviaconductionlossandreducemodule

thermal stress, use multiple vias for interconnection

between top layer and other power layers.

• Do not put via directly on the pad, unless they are

capped or plated over.

• Use a separated SGND ground copper area for com-

ponents connected to signal pins. Connect the SGND

to GND underneath the unit.

• For parallel modules, tie the VOUT,VFB,andCOMPpins

together. Use an internal layer to closely connect these

pins together. The TRACK pin can be tied a common

capacitor for regulator soft-start.

• Bring out test points on the signal pins for monitoring.

Figure13givesagoodexampleoftherecommendedlayout.

Figure 13. Recommended PCB Layout

VOUT1

VOUT2

GND

SGND

CNTRL

4650A F13

GND

VIN

11 12

COUT1

COUT2

CIN1

CIN2

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