LTC2602 datasheet(20/26 Pages) LINER

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LTC2323-16

232316fc

For more information www.linear.com/LTC2323-16

APPLICATIONS INFORMATION

TIMING AND CONTROL

CNV Timing

A rising edge on CNV initiates the acquisition phase and

puts the internal sample-and-hold into the sample mode.

A falling edge on CNV puts the internal sample-and-hold

into the hold mode and starts a conversion cycle. The

CNV pulse must be at least 25ns wide for proper opera-

tion. CNV must be driven by a fast low jitter signal with a

fall time from OVDD to below 100mV of less than 1ns. To

achieve this fast falling edge, the distance from the CNV

source to the CNV pin should be minimized. The trace

for this pulse should be kept as narrow as possible and

routed away from adjacent traces or planes to minimize

capacitance. The drive strength of the gate driving the

CNV line must be sufficient to yield a fast falling edge at

the ADC pin to below 100mV. We recommend the applica-

tions circuit on page 26, which uses a high speed flip-flop

to generate the CNV pulse to the ADC, eliminating the

effect of jitter from the FPGA. If jitter from the FPGA is

not a concern, the flip-flop can be eliminated and replaced

with an inverter such as the NC7SZ04P5X

SCK Serial Data Clock Input

The falling edge of this clock shifts the conversion

result MSB first onto the SDO pins. A 105MHz external

clock must be applied at the SCK pin to achieve 5Msps

throughput.

CLKOUT Serial Data Clock Output

The CLKOUT output provides a skew-matched clock to

latch the SDO output at the receiver. The timing skew

of the CLKOUT and SDO outputs are matched. For high

throughput applications, using CLKOUT instead of SCK to

capture the SDO output eases timing requirements at the

receiver. For low throughput speed applications, CLKOUT+

can be disabled by tying CLKOUT– to OVDD.

Nap/Sleep Modes

Nap mode is a method to save power without sacrificing

power-up delays for subsequent conversions. Sleep mode

has substantial power savings, but a power-up delay is

incurred to allow the reference and power systems to

become valid. To enter nap mode on the LTC2323-16,

the SCK signal must be held high or low and a series

of two CNV pulses must be applied. This is the case for

both CMOS and LVDS modes. The second rising edge of

CNV initiates the nap state. The nap state will persist until

either a single rising edge of SCK is applied, or further

CNV pulses are applied. The SCK rising edge will put the

LTC2323-16 back into the operational (full-power) state.

When in nap mode, two additional pulses will put the

LTC2323-16 in sleep mode. When configured for CMOS

I/O operation, a single rising edge of SCK can return the

LTC2323-16 into operational mode. A 10ms delay is nec-

essary after exiting sleep mode to allow the reference buf-

fer to recharge the external filter capacitor. In LVDS mode,

exit sleep mode by supplying a fifth CNV pulse. The fifth

pulse will return the LTC2323-16 to operational mode,

and further SCK pulses will keep the part from re-entering

nap and sleep modes. The fifth SCK pulse also works in

CMOS mode as a method to exit sleep. In the absence of

SCK pulses, repetitive CNV pulses will cycle the LTC2323-

16 between operational, nap and sleep modes indefinitely.

RefertothetimingdiagramsinFigure 18,Figure 19,Figure 20

and Figure 21 for more detailed timing information about

sleep and nap modes.

FULL POWER MODE

CNV

SCK

HOLD STATIC HIGH OR LOW

NAP MODE

SDO1

SDO2

WAKE ON 1ST SCK EDGE

232316 F18

Figure 18. CMOS and LVDS Mode NAP and WAKE Using SCK

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