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LTC2323-16

232316fc

For more information www.linear.com/LTC2323-16

APPLICATIONS INFORMATION

Figure 22. LTC2323 Using the LVDS Interface

DIGITAL INTERFACE

The LTC2323-16 features a serial digital interface that

is simple and straight forward to use. The flexible OVDD

supply allows the LTC2323-16 to communicate with any

digital logic operating between 1.8V and 2.5V. A 105MHz

external clock must be applied at the SCK pin to achieve

5Msps throughput.

In addition to a standard CMOS SPI interface, the

LTC2323-16 provides an optional LVDS SPI interface to

support low noise digital design. The CMOS/LVDS pin is

used to select the digital interface mode.

The falling edge of SCK outputs the conversion result MSB

first on the SDO pins. CLKOUT provides a skew-matched

clock to latch the SDO output at the receiver. The timing

skew of the CLKOUT and SDO outputs are matched. For

high throughput applications, using CLKOUT instead of

SCK to capture the SDO output eases timing requirements

at the receiver.

In CMOS mode, use the SDO1+, SDO2+ and CLKOUT+

pins as outputs. Use the SCK+ pin as an input. Do not

connect the SDO1–, SDO2–, SCK– and CLKOUT– pins,

as they each have internal pull-down circuitry to OGND.

In LVDS mode, use the SDO1+/SDO1–, SDO2+/SDO2– and

CLKOUT+/CLKOUT– pins as differential outputs. These

pins must be differentially terminated by an external 100Ω

resistor at the receiver (FPGA). The SCK+/SCK– pins are

differential inputs and must be terminated differentially by

an external 100Ω resistor at the receiver (ADC).

2.5V

OVDD

LTC2323-16

FPGA OR DSP

232316 F22

SDO2+

SDO2–

SCK+

SCK–

CLKOUT+

CLKOUT–

SDO1+

SDO1–

CNV

CMOS/LVDS

–

100

–

100

–

100

–

100

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