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PC7447 Datasheet(PDF) 10 Page - ATMEL Corporation |
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PC7447 Datasheet(HTML) 10 Page - ATMEL Corporation |
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10 / 66 page ![]() 10 PC7457/47 [Preliminary] 5345B–HIREL–02/04 Signal Description Figure 2. PC7457 Microprocessor Signal Groups Notes: 1. For the PC7457, there are 19 L3_ADDR signals, (L3_ADDR[0:18]. 2. For the PC7447 and PM7457, there are 5 PLL_CFG signals, (PLL_CFG[0:4]. 18 64 8 1 2 4 2 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 4 1 1 1 1 1 1 1 1 PC7457 L3_ADDR[17:0](1) L3-DATA[0:63] L3_DP[0:7] L3_VSEL L3_CLK[0:1] L3_ECHO_CLK[0:3] L3_CNTL[0:1] INT SMI MCP SRESET HRESET CKSTP_IN CKSTP_OUT TBEN QREQ QACK BVSEL BMODE[0:1] PMON_IN PMON_OUT SYSCLK PLL_CFG[0:3](2) PLL_EXT EXT_QUAL CLK_OUT TCK TDI TDO TMS TRST BR BG A[0:35] AP[0:4] TS TT[0:4] TBST TSIZ[0:2] GBL WT CI AACK ARTRY SHD0/SHD1 HIT DBG DTI[0:3] DRDY D[0:63] DP[0:7] TA TEA 1 1 36 5 1 5 1 3 1 1 1 1 1 2 1 1 4 1 64 8 1 1 Address Arbitration Address Transfer Address Transfer Attributes Address Transfer Termination Data Arbitration Data Transfer Data Transfer Termination L3 Cache Address/Data L3 Cache Clock/Control Interrupts/Resets Processor Status/Control Clock Control Test Interface (JTAG) AVDD GND VDD OVDD GVDD Note: L3 cache interface is not supported in the PC7441, PC7445, or the PC7447 |
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