PC7447 datasheet(6/66 Pages) ATMEL

6 / 66 page

PC7457/47 [Preliminary]

5345B–HIREL–02/04

Performs alignment, normalization, and precision conversion for floating-

point data

Executes cache control and TLB instructions

Performs alignment, zero padding, and sign extension for integer data

Supports hits under misses (multiple outstanding misses)

Supports both big- and little-endian modes, including misaligned little-endian

accesses

•

Three issue queues FIQ, VIQ, and GIQ can accept as many as one, two, and three

instructions, respectively, in a cycle. Instruction dispatch requires the following:

–

Instructions can be dispatched only from the three lowest IQ entries – IQ0,

IQ1, and IQ2

–

A maximum of three instructions can be dispatched to the issue queues per

clock cycle

–

Space must be available in the CQ for an instruction to dispatch (this

includes instructions that are assigned a space in the CQ but not in an issue

queue)

•

Rename buffers

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16 GPR rename buffers

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16 FPR rename buffers

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16 VR rename buffers

•

Dispatch unit

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Decode/dispatch stage fully decodes each instruction

•

Completion unit

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The completion unit retires an instruction from the 16-entry completion

queue (CQ) when all instructions ahead of it have been completed, the

instruction has finished execution, and no exceptions are pending

–

Guarantees sequential programming model (precise exception model)

–

Monitors all dispatched instructions and retires them in order

–

Tracks unresolved branches and flushes instructions after a mispredicted

branch

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Retires as many as three instructions per clock cycle

•

Separate on-chip L1 Instruction and data caches (Harvard Architecture)

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32 Kbyte, eight-way set-associative instruction and data caches

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Pseudo least-recently-used (PLRU) replacement algorithm

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32-byte (eight-word) L1 cache block

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Physically indexed/physical tags

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Cache write-back or write-through operation programmable on a per-page or

per-block basis

–

Instruction cache can provide four instructions per clock cycle; data cache

can provide four words per clock cycle

–

Caches can be disabled in software

–

Caches can be locked in software

PC7447 Datasheet(PDF) 6 Page - ATMEL Corporation

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