PC7447 datasheet(20/66 Pages) ATMEL

20 / 66 page

PC7457/47 [Preliminary]

5345B–HIREL–02/04

Dynamic Characteristics

This section provides the AC electrical characteristics for the PC7457. After fabrication,

functional parts are sorted by maximum processor core frequency as shown in section

“Clock AC Specifications” and tested for conformance to the AC specifications for that

frequency. The processor core frequency is determined by the bus (SYSCLK) frequency

and the settings of the PLL_CFG[0:4] signals. Parts are sold by maximum processor

core frequency; See “Ordering Information” on page 59.

Clock AC Specifications

Table 8 provides the clock AC timing specifications as defined in Figure 8 and repre-

sents the tested operating frequencies of the devices. The maximum system bus

frequency, f

SYSCLK, given in Table 8 is considered a practical maximum in a typical sin-

gle-processor system. The actual maximum SYSCLK frequency for any application of

the PC7457 will be a function of the AC timings of the PC7457, the AC timings for the

system controller, bus loading, printed-circuit board topology, trace lengths, and so

forth, and may be less than the value given in

Table 8.

Table 8. Clock AC Timing Specifications (See Table 3 on page 12 for Recommended Operating Conditions)

Symbol

Characteristic

Maximum Processor Core Frequency

Unit

600 MHz

867 MHz

1000 MHz

DD = 1.1V

Min

Max

Min

Max

Min

Max

CORE

(1)

Processor frequency

500

600

500

867

500

1000

MHz

fVCO

(1)

VCO frequency

1000

1200

1000

1733

1000

2000

MHz

fSYSCLK

(1)(2)

SYSCLK frequency

167

MHz

SYSCLK

(2)

SYSCLK cycle time

tKR, tKF

(3)

SYSCLK rise and fall time

–

tKHKL/tSYSCLK

(4)

SYSCLK duty cycle measured at OVDD/2

–

SYSCLK jitter(5)(6)

–

±150

–

±150

–

Internal PLL relock time(7)

–100–100

–

µs

Symbol

Characteristic

Maximum Processor Core Frequency

Unit

867 MHz

1000 MHz

1200 MHz

1267 MHz

DD = 1.3V

Min

Max

Min

Max

Min

Max

Min

Max

CORE

(1)

Processor frequency

600

867

600

1000

600

1200

600

1267

MHz

VCO

(1)

VCO frequency

1200

1733

1200

2000

1200

2400

1200

2534

MHz

fSYSCLK

(1)(2)

SYSCLK frequency

167

MHz

SYSCLK

(2)

SYSCLK cycle time

, tKF

(3)

SYSCLK rise and fall time

–

1–1–

tKHKL/

SYSCLK

(4)

SYSCLK duty cycle measured at OV

DD/2

SYSCLK jitter(5)(6)

–±150–

±150–±150

–

±150

Internal PLL relock time(7)

–

100

–

100

–

100

–

100

µs

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