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PC7447 Datasheet(PDF) 33 Page - ATMEL Corporation |
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PC7447 Datasheet(HTML) 33 Page - ATMEL Corporation |
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33 / 66 page  33 PC7457/47 [Preliminary] 5345B–HIREL–02/04 Figure 15 shows the typical connection diagram for the PC7457 interfaced to PB2 SRAMs or Late Write SRAMs. Figure 15. Typical Synchronous 1M Byte L3 Cache Late Write or PB2 Interface Note: 1. Or as recommended by SRAM manufacturer for single-ended clocking. L3_ADDR[16:0] L3_CNTL[0] SA[16:0] K K SS SW ZZ G SRAM 0 DQ[0:17] DQ[18:36 ] L3_CNTL[1] GVDD/2 /2 (1) GVDD/2 (1) GND GND SRAM 1 GND GND L3_CLK[0] L3_CLK[1] L3_ECHO_CLK[0] L3_ECHO_CLK[1] L3_ECHO_CLK[2] PC7457 L3_ECHO_CLK[3] SA[16:0] K K SS SW ZZ G DQ[0:17] DQ[18:36] Denotes Receive (SRAM to PC7457) Aligned Signals Denotes Transmit (PC7457 to SRAM) Aligned Signals {L3_DATA[0:15], L3_DP[0:1]} {L3_DATA[16:31], L3_DP[2:3]} {L3_DATA[32:47], L3_DP[4:5]} {L3_DATA[48:63], L3_DP[6:7]} |
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