PC7447 datasheet(52/66 Pages) ATMEL

52 / 66 page

PC7457/47 [Preliminary]

5345B–HIREL–02/04

Notes:

1. PLL_CFG[0:4] settings not listed are reserved.

2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core, or VCO

frequencies which are not useful, not supported, or not tested for by the PC7455; See “Clock AC Specifications” on page 20.

for valid SYSCLK, core, and VCO frequencies.

3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly and the PLL is disabled. However, the

bus interface unit requires a 2x clock to function. Therefore, an additional signal, EXT_QUAL, must be driven at one-half the

frequency of SYSCLK and offset in phase to meet the required input setup tIVKH and hold time tIXKH (see Table 9 on page

22). The result is that the processor bus frequency is one-half SYSCLK while the internal processor is clocked at SYSCLK

frequency. This mode is intended for factory use and emulator tool use only.

Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.

PLL_CFG[0:4]

Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)

Bus-to-Core

Multiplier

Core-to-VCO

Multiplier

Bus (SYSCLK) Frequency

33.3

MHz

66.6

MHz

100

MHz

133

MHz

167

MHz

10011

11x

733

(1466)

825

(1650)

913

(1826)

1100

(2200)

00000

11.5x

766

(532)

863

(1726)

955

(1910)

1150

(2300)

10111

12x

600

(1200)

800

(1600)

900

(1800)

996

(1992)

1200

(2400)

11111

12.5x

600

(1200)

833

(1666)

938

(1876)

1038

(2076)

1250

(2500)

01011

13x

650

(1300)

865

(1730)

975

(1950)

1079

(2158)

11100

13.5x

675

(1350)

900

(1800)

1013

(2026)

1121

(2242)

11001

14x

700

(1400)

933

(1866)

1050

(2100)

1162

(2324)

00011

15x

750

(1500)

1000

(2000)

1125

(2250)

1245

(2490)

11011

16x

800

(1600)

1066

(2132)

1200

(2400)

00001

17x

850

(1900)

1132

(2264)

00101

18x

600

(1200)

900

(1800)

1200

(2400)

00111

20x

667

(1334)

1000

(2000)

01001

21x

700

(1400)

1050

(2100)

01101

24x

800

(1600)

1200

(2400)

11101

28x

933

(1866)

00110

PLL bypass

PLL off, SYSCLK clocks core circuitry directly

11110

PLL off

PLL off, no core clocking occurs

Table 18. PC7457 Microprocessor PLL Configuration Example for 1267 MHz Parts (Continued)

PC7447 Datasheet(PDF) 52 Page - ATMEL Corporation

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