PC7447 datasheet(12/66 Pages) ATMEL

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PC7457/47 [Preliminary]

5345B–HIREL–02/04

7. L3VSEL must be set to 0, such that the bus is in 1.8V mode.

8. L3VSEL must be set to HRESET or 1, such that the bus is in 2.5V mode.

9. Caution: V

IN must not exceed OVDD or GVDD by more than 0.3V at any time including during power-on reset.

10. VIN may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 3.

Recommended

Operating Conditions

Notes:

1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not

guaranteed.

2. This voltage is the input to the filter discussed in Section “PLL Power Supply Filtering” on page 54 and not necessarily the

voltage at the AV

DD pin which may be reduced from VDD by the filter.

3. ¬HRESET is the inverse of HRESET.

Figure 3. Overshoot/Undershoot Voltage

Table 3. Recommended Operating Conditions

(1)

Symbol

Characteristic

Recommended Value

Unit

Min

Max

VDD

Core supply voltage

1.3V ±50 mV or 1.1V ±50 mV

AVDD

(2)

PLL supply voltage

1.3V ±50 mV or 1.1V ±50 mV

Processor bus supply voltage

BVSEL = 0

1.8V ±5%

OVDD

BVSEL = HRESET or OVDD

2.5V ±5%

GVDD

L3 bus supply voltage

L3VSEL = 0

1.8V ±5%

L3VSEL = HRESET or GV

2.5V ±5%

GVDD

(3)

L3VSEL = ¬HRESET

1.5V ±5%

VIN

Input voltage

Processor bus

GND

OVDD

L3 bus

GND

VIN

JTAG signals

GND

OVDD

Die-junction temperature

-55

125

°C

GND

GND – 0.3V

GND – 0.7V

Not to exceed 10% of tSYSCLK

OVDD/GVDD + 20%

OVDD/GVDD + 5%

OVDD/GVDD

VIH

VIL

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