EM78P568

8-bit OTP Micro-controller

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* This specification are subject to be changed without notice.

15

01/31/2004

V4.7

Sub-clock

32.768kHz

switch

0

1

System clock

PLL circuit

447.8293kHz ~17.9132MHz

ENPLL

CLK2 ~ CLK0

Fig.4 The relation between 32.768kHz and PLL

Bit 7(IDLE) : Sleep mode or IDLE mode control after using "SLEP" instruction.

0/1

SLEEP mode/IDLE mode.

This bit will decide SLEP instruction which mode to go.

The status after wake-up and the wake-up sources list as the table below.

Wakeup signal

SLEEP mode

IDLE mode

RA(7,6)=(0,0)

+ SLEP

RA(7,6)=(1,0)

+ SLEP

TCC time out

IOCF bit0=1

No function

(1) Wake-up

(2) Jump to SLEP next instruction

COUNTER1 time out

IOCF bit1=1

No function

(1) Wake-up

(2) Jump to SLEP next instruction

COUNTER2 time out

IOCF bit2=2

No function

(1) Wake-up

(2) Jump to SLEP next instruction

WDT time out

Reset and jump to

address 0

(1) Wake-up

(2) Next instruction

PORT8(0~3)

RE PAGE0 bit3 or

bit4 or bit5 or bit6 = 1

Reset and Jump to

address 0

(1) Wake-up

(2) Jump to SLEP next instruction

PORT7(0~3)

IOCF bit3 or bit4 or

bit5 or bit7=1

Reset and Jump to

address 0

(1) Wake-up

(2) Jump to SLEP next instruction

<Note> PORT70 's wakeup function is controlled by IOCF bit 3. It's falling edge or rising edge trigger

(controlled by CONT register bit7).

PORT7(1~3) 's wakeup functions are controlled by IOCF bit (4,5,7). They are falling edge trigger.

PORT80~PORT83’s wakeup function are controlled by RE PAGE0 bit 0 ~ bit 3. They are falling

edge trigger.