EM78P568

8-bit OTP Micro-controller

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* This specification are subject to be changed without notice.

38

01/31/2004

V4.7

VII.4 I/O Port

The I/O registers are bi-directional tri-state I/O ports. The I/O ports can be defined as "input" or "output" pins by

the I/O control registers under program control. The I/O data registers and I/O control registers are both readable

and writable. The I/O interface circuit is shown as follows.

Fig.15 The circuit of I/O port and I/O control register

VII.5 RESET

The RESET can be caused by

(1) Power on voltage detector reset (/POVD) and power on reset

(2) WDT timeout. (if enabled and in GREEN or NORMAL mode)

(3) /RESET pin pull low

<Note> At case (1), /POVD is controlled by CODE OPTION. If you enable /POVD, CPU will reset at under

1.8V and CPU will consume more current about 5uA. It is used for low voltage reset/ And the power-on

reset is a circuit which is always enabled and only works on initially power-on reset. It will reset CPU at

about 1.4V and consume about 0.5uA.

Once the RESET occurs, the following functions are performed.

• The oscillator is running, or will be started.

• The Program Counter (R2) is set to all "0".

• When power on, the upper 3 bits of R3 and the upper 2 bits of R4 are cleared.

• The Watchdog timer and prescaler counter are cleared.

• The Watchdog timer is disabled.

• The CONT register is set to all "1"

• The other register (bit 7 ~ bit 0) defult values are as follows.

M

U

X

0

1

PDRD

PDWR

CLK

C

L

P

R

D

Q

Q

CLK

C

L

P

R

D

Q

Q

PCWR

IOD

PCRD

PORT