EM78P568

8-bit OTP Micro-controller

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* This specification are subject to be changed without notice.

10

01/31/2004

V4.7

Fig.3 Program counter organization

R3 (Status, Page selection)

(Status flag, Page selection bits)

7

6

5

4

3

2

1

0

RPAGE2

RPAGE

IOCPAGE

T

P

Z

DC

C

R/W-0

R/W-0

R/W-0

R

R

R/W

R/W

R/W

Bit 0(C) : Carry flag

Bit 1(DC) : Auxiliary carry flag

Bit 2(Z) : Zero flag

Bit 3(P) : Power down bit

Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command.

Bit 4(T) : Time-out bit

Set to 1 by the "SLEP" and "WDTC" command, or during power up and reset to 0 by WDT timeout.

EVENT

T

P

REMARK

WDT wake up from sleep mode

0

0

WDT time out (not sleep mode)

0

1

/RESET wake up from sleep

1

0

Power up

1

1

Low pulse on /RESET

x

X

x : don't care

Bit 5(IOCPAGE) : change IOC5 ~ IOCE to another page

0/1

IOC page0 / IOC page1

Please refer to VII.1 Operational registers for detail IOC PAGE register configuration.

Bit 6 ~ Bit 7 (RPAGE0 ~ RPAGE1) : change R5 ~ RE to another page

(RPAGE1,RPAGE0)

R page # selected

(0,0)

R page 0

(0,1)

R page 1

(1,0)

R page 2

(1,1)

R page 3

PC

A13 A12 A11 A10

A9 A8

A7~A0

0000

PAGE0 0000~03FF

0001

PAGE1 0400~07FF

1110

PAGE14 3800~3BFF

1111

PAGE15 3C00~3FFF

0010

PAGE2 0800~0BFF

STACK1

STACK2

STACK3

STACK4

STACK5

STACK6

STACK7

STACK8

STACK9

STACK10

STACK11

STACK12

STACK13

STACK14

STACK15

STACK16

CALL and

INTERRUPT

RET

RETL

RETI

ACC,R3,R5(PAGE)

R5(PAGE)

store

restore