EM78P568

8-bit OTP Micro-controller

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* This specification are subject to be changed without notice.

39

01/31/2004

V4.7

Operation registers :

Address

R register

PAGE0

R register

PAGE1

R register

PAGE2

IOC register

PAGE0

IOC register

PAGE1

0x4

00xxxxxx

0x5

xxxx0000

xxxx0000

111x0000

00000000

0x6

xxxxxxxx

xxxxxxxx

11111111

00000000

0x7

xxxxxxxx

xxxxxx00

11111111

00000000

0x8

xxxxxxxx

00000000

11111111

00000000

0x9

xxxxxxxx

xxxxxxxx

11111111

00000000

0xA

00011x00

11111111

0xxxxxxx

00000000

00000xxx

0xB

xxxxxxxx

11111111

0xC

xxxxxxxx

00000000

11111111

000000x0

0xD

0xxxx000

00000000

00000000

00000000

0xE

xxxx0000

11111111

0000x000

00000000

0xF

00000000

00000000

VII.6 Wake-up

The controller has two types of sleep mode for power saving :

(1) SLEEP mode, RA(7) = 0 + "SLEP" instruction

The controller will turn off all the CPU and crystal. Other circuit with power control like key tone control or

PLL control (which has enable register), user has to turn it off by software.

(2) IDLE mode, RA(7) = 1 + "SLEP" instruction.

The controller will turn CPU off, but the crystal.

Wake-up from SLEEP mode

(1) WDT time out

(2) External interrupt

(3) /RESET pull low

All these cases will reset controller , and run the program at address zero. The status just like the power on reset.

Be sure to enable circuit at case (1) or (2).

Wake-up from IDLE mode

(1)WDT time out

(2) external interrupt

(3) internal interrupt like counters

All these cases, user has to enable circuit before entering IDLE mode. After wake-up, all the register will keep

values just like into "SLEP" instruction before.

At case (2) or (3), controller will wake up and jump to address 0x08 for interruption sub-routine. After finishing

sub-routine ("RETI" instruction), program will jump to the next instruction from "SLEP" instruction.

VII.7 Interrupt

RF is the interrupt status register which records the interrupt request in flag bit. IOCF is the interrupt mask

register. Global interrupt is enabled by ENI instruction and is disabled by DISI instruction. When one of the

interrupts (when enabled) generated, will cause the next instruction to be fetched from address 008H. Once in the

interrupt service routine, the source of the interrupt can be determined by polling the flag bits in the RF register.