EM78P568

8-bit OTP Micro-controller

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* This specification are subject to be changed without notice.

19

01/31/2004

V4.7

30

01010001

173.8

81

172.773

31

01001110

179.9

78

179.419

32

01001100

183.5

76

184.140

33

01001011

186.2

75

186.595

34

01001010

189.9

74

189.117

35

01001001

192.8

73

191.708

36

01000111

196.6

71

197.108

37

01000110

199.5

70

199.924

38

01000101

203.5

69

202.821

39

01000100

206.5

68

205.804

40

01000010

210.7

66

212.040

41

01000000

218.1

64

218.667

42

00111110

225.7

62

225.720

43

00111101

229.1

61

229.421

44

00111100

233.6

60

233.244

45

00111010

241.8

58

241.287

46

00111000

250.3

56

249.905

47

00110111

254.1

55

254.448

RF (Interrupt status)

(Interrupt status register)

7

6

5

4

3

2

1

0

INT3

DETO

INT2

INT1

INT0

CNT2

CNT1

TCIF

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

"1" means interrupt request, "0" means non-interrupt

Bit 0(TCIF) : TCC timer overflow interrupt flag

Set when TCC timer overflows.

Bit 1(CNT1) : counter1 timer overflow interrupt flag

Set when counter1 timer overflows.

Bit 2(CNT2) : counter2 timer overflow interrupt flag

Set when counter2 timer overflows.

Bit 3(INT0) : external INT0 pin interrupt flag

If PORT70 has a falling edge/rising edge (controlled by CONT register) trigger signal, CPU will set this bit.

Bit 4(INT1) : external INT1 pin interrupt flag

If PORT71 has a falling edge trigger signal, CPU will set this bit.

Bit 5(INT2) : external INT2 pin interrupt flag

If PORT72 has a falling edge trigger signal, CPU will set this bit.

Bit 6(DETO) : CTCSS tone detection interrupt flag

If CTCSS detection output signal(R7 PAGE1 bit 6)

has an edge signal (falling edge, falling and rising

edge), CPU will set this bit.

Bit 7(INT3) : external INT3 pin interrupt flag

If PORT73 has a falling edge trigger signal, CPU will set this bit.

<Note> IOCF is the interrupt mask register. User can read and clear.