TPS61372 datasheet(23/35 Pages) TI1

23 / 35 page

ESR

OUT

ESR

OUT

p ´

OUT

p ´

DOWN

PS C

DOWN

(f )

log(G

)

(f )

= -

p ´

TPS61372

www.ti.com

SLVSEE7 – JUNE 2018

Product Folder Links: TPS61372

Submit Documentation Feedback

where

•

CP is the pole capacitor compensation

•

RC is the resistor of the compensation network

(32)

(33)

9.2.3.4.2

Loop Compensation Design Steps

With the small signal models coming out, the next step is to calculate the compensation network parameters with

the given inductor and output capacitance.

1. Set the Cross Over Frequency, ƒC

–

The first step is to set the loop crossover frequency, ƒC. The higher crossover frequency, the faster the

loop response is. It is generally accepted that the loop gain cross over no higher than the lower of either

1/10 of the switching frequency, ƒSW, or 1/5 of the RHPZ frequency, ƒRHPZ. Then calculate the loop

compensation network values of RC, CC, and CP by following below eqµAtions.

2. Set the Compensation Resistor, RC

–

By placing ƒZ below ƒC, for frequencies above ƒC, RC | | REA ~= RC and so RC × GEA sets the

compensation gain. Setting the compensation gain, KCOMP-dB, at ƒZ, results in the total loop gain, T(s) =

GPS(s) × HEA(s) × He(s) being zero at ƒC.

–

Therefore, to approximate a single-pole roll-off up to fP2, rearrange Equation 30 to solve for RC so that

the compensation gain, KEA, at fC is the negative of the gain, KPS, read at frequency fC for the power

stage bode plot or more simply:

where

•

KEA is gain of the error amplifier network

•

KPS is the gain of the power stage

•

GEA is the amplifier’s trans-conductance, the typical value of GEA = 175 µA / V

(34)

3. Set the compensation zero capacitor, CC

–

Place the compensation zero at the power stage ROUT ,COUT pole’s position, so to get:

(35)

–

Set ƒZ = ƒP, and get the

(36)

4. Set the compensation pole capacitor, CP

–

Place the compensation pole at the zero produced by the RESR and the COUT, it is useful for canceling

unhelpful effects of the ESR zero.

(37)

(38)

–

Set ƒP2 = ƒESR, and get the

(39)

–

If the calculated value of CP is less than 10 pF, it can be neglected.

Designing the loop for greater than 45° of phase margin and greater than 6-dB gain margin eliminates output

voltage ringing during the line and load transient. The RC = 61.9 kΩ , CC = 680 pF for this design example.

TPS61372 Datasheet(PDF) 23 Page - Texas Instruments

TPS61372 Datasheet(HTML) 23 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

Datasheet Download

Link URL