LPC81XM datasheet(19/78 Pages) NXP

19 / 78 page

LPC81XM

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Product data sheet

Rev. 4.6 — 4 April 2018

19 of 78

NXP Semiconductors

LPC81xM

32-bit ARM Cortex-M0+ microcontroller

– The pattern match engine does not facilitate wake-up.

8.12 USART0/1/2

Remark: USART0 and USART1 are available on all LPC800 parts. USART2 is available

on parts LPC812M101JTB16, LPC812M101JDH16, and LPC812M101JDH20 only.

All USART functions are movable functions and are assigned to pins through the switch

matrix.

8.12.1 Features

• Maximum bit rates of 1.875 Mbit/s in asynchronous mode and 10 Mbit/s in

synchronous mode for USART functions connected to all digital pins except PIO0_10

and PIO0_11.

• 7, 8, or 9 data bits and 1 or 2 stop bits

• Synchronous mode with master or slave operation. Includes data phase selection and

continuous clock option.

• Multiprocessor/multidrop (9-bit) mode with software address compare. (RS-485

possible with software address detection and transceiver direction control.)

• Parity generation and checking: odd, even, or none.

• One transmit and one receive data buffer.

• RTS/CTS for hardware signaling for automatic flow control. Software flow control can

be performed using Delta CTS detect, Transmit Disable control, and any GPIO as an

RTS output.

• Received data and status can optionally be read from a single register

• Break generation and detection.

• Receive data is 2 of 3 sample "voting". Status flag set when one sample differs.

• Built-in Baud Rate Generator.

• A fractional rate divider is shared among all UARTs.

• Interrupts available for Receiver Ready, Transmitter Ready, Receiver Idle, change in

receiver break detect, Framing error, Parity error, Overrun, Underrun, Delta CTS

detect, and receiver sample noise detected.

• Separate data and flow control loopback modes for testing.

• Supported by on-chip ROM API.

8.13 SPI0/1

Remark: SPI0 is available on all LPC800 parts. SPI1 is available on parts

LPC812M101JDH16 and LPC812M101JDH20 only.

All SPI functions are movable functions and are assigned to pins through the switch

matrix.

8.13.1 Features

• Maximum data rates of 30 Mbit/s in master mode and 25 Mbit/s in slave mode for SPI

functions connected to all digital pins except PIO0_10 and PIO0_11.

LPC81xM Datasheet(PDF) 19 Page - NXP Semiconductors

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