LPC81XM datasheet(26/78 Pages) NXP

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LPC81XM

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Product data sheet

Rev. 4.6 — 4 April 2018

26 of 78

NXP Semiconductors

LPC81xM

32-bit ARM Cortex-M0+ microcontroller

divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the

minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle.

The PLL is turned off and bypassed following a chip reset and may be enabled by

software. The program must configure and activate the PLL, wait for the PLL to lock, and

then connect to the PLL as a clock source. The PLL settling time is nominally 100

s.

8.20.4 Clock output

The LPC81xM features a clock output function that routes the IRC, the SysOsc, the

watchdog oscillator, or the main clock to the CLKOUT function. The CLKOUT function can

be connected to any digital pin through the switch matrix.

8.20.5 Wake-up process

The LPC81xM begin operation at power-up by using the IRC as the clock source. This

allows chip operation to resume quickly. If the SysOsc, the external clock source, or the

PLL is needed by the application, software must enable these features and wait for them

to stabilize before they are used as a clock source.

8.20.6 Power control

The LPC81xM supports the ARM Cortex-M0 Sleep mode. The CPU clock rate may also

be controlled as needed by changing clock sources, reconfiguring PLL values, and/or

altering the CPU clock divider value. This allows a trade-off of power versus processing

speed based on application requirements. In addition, a register is provided for shutting

down the clocks to individual on-chip peripherals, allowing to fine-tune power

consumption by eliminating all dynamic power use in any peripherals that are not required

for the application. Selected peripherals have their own clock divider which provides even

better power control.

8.20.6.1

Power profiles

The power consumption in Active and Sleep modes can be optimized for the application

through simple calls to the power profile API. The API is accessible through the on-chip

ROM.

The power configuration routine configures the LPC81xM for one of the following power

modes:

• Default mode corresponding to power configuration after reset.

• CPU performance mode corresponding to optimized processing capability.

• Efficiency mode corresponding to optimized balance of current consumption and CPU

performance.

• Low-current mode corresponding to lowest power consumption.

In addition, the power profile includes routines to select the optimal PLL settings for a

given system clock and PLL input clock.

8.20.6.2

Sleep mode

When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep

mode does not need any special sequence but re-enabling the clock to the ARM core.

LPC81xM Datasheet(PDF) 26 Page - NXP Semiconductors

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