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AD9574 Datasheet(PDF) 32 Page - Analog Devices

Part # AD9574
Description  Ethernet/Gigabit Ethernet Clock Generator
PDF  35 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9574 Datasheet(HTML) 32 Page - Analog Devices

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AD9574
Data Sheet
Rev. B | Page 32 of 35
Rx
Rx
REFERENCE
MONITOR
AD9574
PFD/
CP
LF
VCO
PPR CONTROL
×1/×2
×1/×2
REF0_P
REF0_N
REF1_P
REF1_N
MCLK_P
MCLK_N
REF_ACT
REF_SW
REF_FHI
REF_FLO
REF_SEL
REFMON
OUT0_N
OUT0_P
OUT1_N
OUT1_P
OUT2_N
OUT2_P
OUT3_N
OUT3_P
OUT4_N
OUT4_P
OUT5_N
OUT5_P
OUT6_N
OUT6_P
LD
LF
PROGRAMMING
RESISTORS
3.3V
LDO_BYP
1nF
470nF
LOR
LD
XO
47
41
7
27
26
24
19
1
2
6
5
45
46
48
25
35
34
44
43
11
12
38
37
39
40
29
28
32
33
22
21
10
9
14
15
16
Figure 27. Single Oscillator Reference Input Application Diagram
INTERFACING TO LVDS AND HSTL CLOCK
OUTPUTS
LVDS and HSTL both employ a differential output driver. The
recommended termination circuit for LVDS and HSTL drivers
appears in Figure 28.
HSTL/LVDS
DRIVER
100
Ω
RECEIVER
INDEPENDENT
UNCOUPLED 50
Ω
TRANSMISSION LINES
Figure 28. LVDS or HSTL Output Termination
See the AN-586 Application Note for more information about
LVDS.
INTERFACING TO HCSL CLOCK OUTPUTS
HCSL uses a differential open-drain architecture. The open-
drain architecture necessitates the use of an external termination
resistor. Figure 29 shows the typical method for interfacing to
HCSL drivers.
HCSL
50
Ω
50
Ω
RECEIVER
INDEPENDENT
UNCOUPLED 50
Ω
TRANSMISSION LINES
Figure 29. HCSL Output Termination
In some cases, the fast switching capability of HCSL drivers
results in overshoot and ringing. The alternative HCSL interface
shown in Figure 30 can mitigate this problem via a small series
resistor, typically in the 10 Ω to 30 Ω range.
HCSL
50
Ω
50
Ω
INDEPENDENT
UNCOUPLED 50
Ω
TRANSMISSION LINES
RECEIVER
10
Ω TO 30Ω
10
Ω TO 30Ω
Figure 30. Alternate HCSL Output Termination



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