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AD9574 Datasheet(PDF) 30 Page - Analog Devices

Part # AD9574
Description  Ethernet/Gigabit Ethernet Clock Generator
PDF  35 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9574 Datasheet(HTML) 30 Page - Analog Devices

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AD9574
Data Sheet
Rev. B | Page 30 of 35
APPLICATIONS INFORMATION
DUAL OSCILLATOR REFERENCE INPUT
APPLICATION
Figure 24 depicts a typical application diagram using two
crystal oscillators (XOs) as the reference inputs. A stable
oscillator source supplies the MCLK_x inputs and serves as the
timing reference for the on-board reference monitoring
function. A field-programmable gate array (FPGA) handles the
control interface for monitoring the status of the references and
the PLL (lock detector) and for switching between references as
required. The FPGA also controls the on/off state of the
reference oscillators, which provides for shutting down a faulty
reference or for keeping a redundant reference turned off until
needed. The general configuration of the AD9574 is set via a
group of resistors that establish the desired PPRx states.
Although Figure 24 shows XOs with differential outputs, single-
ended XOs can be substituted by connecting the XO output to
the REFx_P pin and a 0.1 nF capacitor from the REFx_N pin to
GND.
Rx
Rx
REFERENCE
MONITOR
AD9574
PFD/
CP
LF
VCO
PPR CONTROL
×1/×2
×1/×2
REF0_P
REF0_N
REF1_P
REF1_N
MCLK_P
MCLK_N
REF_ACT
REF_SW
REF_FHI
REF_FLO
REF_SEL
REFMON
OUT0_N
OUT0_P
OUT1_N
OUT1_P
OUT2_N
OUT2_P
OUT3_N
OUT3_P
OUT4_N
OUT4_P
OUT5_N
OUT5_P
OUT6_N
OUT6_P
LD
LF
LDO_BYP
1nF
470nF
47
41
7
27
26
24
19
1
2
6
5
45
46
48
25
35
34
44
43
11
12
38
37
39
40
29
28
32
33
22
21
10
9
14
15
16
STABLE
REFERENCE
FPGA
XO
XO
ON/OFF
CONTROL
PROGRAMMING
RESISTORS
3.3V
Figure 24. Dual Oscillator Reference Input Application Diagram



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