| Electronic Components Datasheet Search |
|
AD9574 Datasheet(PDF) 3 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD9574 Datasheet(HTML) 3 Page - Analog Devices |
|
3 / 35 page ![]() Data Sheet AD9574 Rev. B | Page 3 of 35 SPECIFICATIONS OUT0 CHANNEL ABSOLUTE CLOCK JITTER Typical values applicable under the conditions of VS = 3.3 V, TA = 25°C, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments HIGH SPEED TRANSCEIVER LOGIC (HSTL) INTEGRATED JITTER Jitter integration bandwidth = 12 kHz to 5 MHz 19.44 MHz Output 0.196 ps rms 25 MHz Output 0.179 ps rms 38.88 MHz Output 1.943 ps rms 50 MHz Output 1.523 ps rms 3.3 V CMOS INTEGRATED JITTER Jitter integration bandwidth = 12 kHz to 5 MHz 19.44 MHz Output 0.204 ps rms 25 MHz Output 0.178 ps rms 38.88 MHz Output 1.969 ps rms 50 MHz Output 1.446 ps rms OUT1 CHANNEL ABSOLUTE CLOCK JITTER Typical values applicable under the conditions of VS = 3.3 V, TA = 25°C, unless otherwise noted. Table 2. Parameter Min Typ Max Unit Test Conditions/Comments HSTL INTEGRATED JITTER Jitter integration bandwidth = 12 kHz to 5 MHz 19.44 MHz Output 0.175 ps rms 25 MHz Output 0.153 ps rms 3.3 V CMOS INTEGRATED JITTER Jitter integration bandwidth = 12 kHz to 5 MHz 19.44 MHz Output 0.184 ps rms 25 MHz Output 0.160 ps rms OUT2 AND OUT3 CHANNELS ABSOLUTE CLOCK JITTER Typical values applicable under the conditions of VS = 3.3 V, TA = 25°C, unless otherwise noted. Frequency multiplier (×2) at PLL input enabled. Table 3. Parameter Min Typ Max Unit Test Conditions/Comments HSTL INTEGRATED JITTER Jitter Integration Bandwidth = 10 kHz to 10 MHz 155.52 MHz Output 0.244 ps rms 156.25 MHz Output 0.234 ps rms 160 MHz Output 1.290 ps rms Frequency multiplier (×2) at PLL input bypassed Jitter Integration Bandwidth = 12 kHz to 20 MHz 155.52 MHz Output 0.470 ps rms 156.25 MHz Output 0.243 ps rms 160 MHz Output 1.329 ps rms Frequency multiplier (×2) at PLL input bypassed Jitter Integration Bandwidth = 1.875 MHz to 20 MHz 155.52 MHz Output 0.409 ps rms 156.25 MHz Output 0.100 ps rms 160 MHz Output 1.257 ps rms Frequency multiplier (×2) at PLL input bypassed |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |