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AD9574 Datasheet(PDF) 3 Page - Analog Devices

Part # AD9574
Description  Ethernet/Gigabit Ethernet Clock Generator
PDF  35 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9574 Datasheet(HTML) 3 Page - Analog Devices

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Data Sheet
AD9574
Rev. B | Page 3 of 35
SPECIFICATIONS
OUT0 CHANNEL ABSOLUTE CLOCK JITTER
Typical values applicable under the conditions of VS = 3.3 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
HIGH SPEED TRANSCEIVER LOGIC
(HSTL) INTEGRATED JITTER
Jitter integration bandwidth = 12 kHz to 5 MHz
19.44 MHz Output
0.196
ps rms
25 MHz Output
0.179
ps rms
38.88 MHz Output
1.943
ps rms
50 MHz Output
1.523
ps rms
3.3 V CMOS INTEGRATED JITTER
Jitter integration bandwidth = 12 kHz to 5 MHz
19.44 MHz Output
0.204
ps rms
25 MHz Output
0.178
ps rms
38.88 MHz Output
1.969
ps rms
50 MHz Output
1.446
ps rms
OUT1 CHANNEL ABSOLUTE CLOCK JITTER
Typical values applicable under the conditions of VS = 3.3 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
HSTL INTEGRATED JITTER
Jitter integration bandwidth = 12 kHz to 5 MHz
19.44 MHz Output
0.175
ps rms
25 MHz Output
0.153
ps rms
3.3 V CMOS INTEGRATED JITTER
Jitter integration bandwidth = 12 kHz to 5 MHz
19.44 MHz Output
0.184
ps rms
25 MHz Output
0.160
ps rms
OUT2 AND OUT3 CHANNELS ABSOLUTE CLOCK JITTER
Typical values applicable under the conditions of VS = 3.3 V, TA = 25°C, unless otherwise noted. Frequency multiplier (×2) at PLL input
enabled.
Table 3.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
HSTL INTEGRATED JITTER
Jitter Integration Bandwidth = 10 kHz to 10 MHz
155.52 MHz Output
0.244
ps rms
156.25 MHz Output
0.234
ps rms
160 MHz Output
1.290
ps rms
Frequency multiplier (×2) at PLL input bypassed
Jitter Integration Bandwidth = 12 kHz to 20 MHz
155.52 MHz Output
0.470
ps rms
156.25 MHz Output
0.243
ps rms
160 MHz Output
1.329
ps rms
Frequency multiplier (×2) at PLL input bypassed
Jitter Integration Bandwidth = 1.875 MHz to 20 MHz
155.52 MHz Output
0.409
ps rms
156.25 MHz Output
0.100
ps rms
160 MHz Output
1.257
ps rms
Frequency multiplier (×2) at PLL input bypassed



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