AD9574 datasheet(29/35 Pages) AD

29 / 35 page

Data Sheet

AD9574

Rev. B | Page 29 of 35

The PFD, charge pump, and loop filter work together to tune

the VCO output frequency according to the phase difference

of the clock edges at the input to the PFD. The closed-loop

configuration gradually causes the phase difference at the PFD

input to settle near zero and the VCO output frequency to settle

to a value of N times the PFD input frequency (N is the

feedback divider value). Based on the PPRx pin settings, the

AD9574 automatically selects the value of N and the prescaler

value to yield one of three VCO frequencies (2488 MHz,

2500 MHz, or 2560 MHz) per Table 22.

The loop filter consists of a partially integrated third-order RC

network with an external network connected between the LF

and LDO_BYP pins. The external network consists of a 1 nF or

2 nF capacitor or a series connected 2 nF capacitor, C, and

4.75 kΩ resistor, R (see Table 32). The loop filter components,

charge pump current, feedback divider, and VCO gain define

the bandwidth of the PLL according to Table 22. The device

automatically adjusts the internal components per the PPRx

settings to maintain an approximately constant loop bandwidth.

Table 32. External Loop Filter Components

PPR1 State

External Components

C = 1 nF

C = 2 nF

C = 1 nF

C = 2 nF

C = 1 nF

C = 2 nF

C = 2 nF in series with R = 4.75 kΩ

Figure 23 is a diagram of the loop filter portion of the PLL.

CHARGE

PUMP

INTEGRATED LOOP FILTER

VCO

EXTERNAL

COMPONENTS

LDO_BYP

Figure 23. PLL Loop Filter Detail

The AD9574 also provides a digital lock detect output signal at

the LD pin, which indicates (active high) when the device

considers the PFD input phase differential to have stabilized

near zero.

The OUT2 through OUT6 channels are static (outputs do not

toggle) while the PLL is unlocked (that is, while the LD pin is

Logic 0).

OUTPUT DRIVERS

The output channels of the AD9574 offer the flexibility of a

variety of drive formats, including HSTL, HCSL, LVDS, and

CMOS. Each channel offers a subset of these formats (see Table 33).

Table 33. Output Drive Formats

Output

Channel

Format

HSTL

HCSL

LVDS

CMOS

3.3 V

1.8 V

Yes

OUTPUT CLOCKS

The seven output clock channels (OUT0 through OUT6)

provide two different frequency translation functions. OUT0

and OUT1 offer a replica of the reference frequency (with a

frequency doubling option for OUT0), whereas OUT2 through

OUT6 offer rational frequency translations by means of an

integrated integer-N PLL. Table 34 shows a summary of the

available frequencies for each output channel (in units of MHz).

The indicated reference to output frequency translations

depends on the results of a PPRx scan (see the PPRx Pins

section for details).

Table 34. Output Frequencies

fREF

Output (MHz)

156.25

100

33.33

125

66.67

312.5

133.3

160

19.44

155.52

38.88

N/A1

77.76

1 N/A means not applicable.

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