AD9574 datasheet(21/35 Pages) AD

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Data Sheet

AD9574

Rev. B | Page 21 of 35

THEORY OF OPERATION

PLL

REF0_P

REF0_N

REF1_P

REF1_N

MCLK_P

MCLK_N

REF_ACT

REF_SW

REF_FHI

REF_FLO

REF.

SWITCH

REF_SEL

PPR CONTROL

1/2, 1, 5/2, 5

PFD

LOOP

FILTER

LOCK

DET

VCO

50, 64, 100,

128, 256, 512

RESET

3.3V CMOS

HSTL

3.3V CMOS

×2

OUT2_N

OUT2_P

OUT3_N

OUT3_P

HSTL

OUT4_N

OUT4_P

LVDS/HCSL/HSTL

OUT5_N

OUT5_P

LVDS/HCSL/HSTL

OUT6_P

OUT6_N

3.3V CMOS

LVDS

3.3V CMOS

1.8V

CMOS

1.8V

CMOS

2, 4, 5, 8, 16

3.75

2488MHz

2500MHz

2560MHz

REFMON

AD9574

Figure 20. Detailed Block Diagram

OVERVIEW

Figure 20 shows a block diagram of the AD9574. The AD9574

accepts a 19.44 MHz or 25 MHz reference clock at the REF0_x

and/or REF1_x inputs. It also accepts a 0.008 MHz, 10 MHz,

19.44 MHz, 25 MHz, or 38.88 MHz monitor input clock at the

MCLK_x input. The monitor input clock serves as a stable

frequency reference for the internal reference frequency

monitor of the device. The input clock receivers provide

differential or single-ended input configurations.

The AD9574 provides up to seven output channel clocks

(OUT0 to OUT6). The OUT0 and OUT1 channels provide a

replica of the REF0 or REF1 channel frequency with a

frequency doubling option for OUT0. The OUT2 through

OUT6 channels provide various output frequencies by means of

an integrated PLL and divider chains. The output clock drivers

provide for a variety of modes including LVDS, HSTL, HCSL,

1.8 V CMOS, and 3.3 V CMOS, although not all modes are

available at every output.

The integrated PLL provides the necessary frequency translations.

The divider block at the input to the PLL consists of a ×2 multiplier,

a divide-by-5, and a multiplexer configured to provide the four

possible divide values (1/2, 1, 5/2, or 5), as shown in Figure 20.

PPRx PINS

The AD9574 makes use of seven PPRx pins to configure the

device. Internal circuitry scans the PPRx pins for the presence

of resistor terminations and configures the device accordingly.

A PPRx pin scan occurs automatically as part of the power-on

reset sequence (see the Power-On Reset (POR) section) or

following assertion of the RESET pin.

Each PPRx pin controls a specific function or functional block

within the device (see Table 19). The configuration of a functional

block depends on the scanned state of the corresponding PPRx pin.

The scan of a PPRx pin identifies one of eight possible states based

on an external pull-up or pull-down resistor (maximum 10%

tolerance) per Table 20.

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