AD9574 datasheet(11/35 Pages) AD

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Data Sheet

AD9574

Rev. B | Page 11 of 35

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

Minimal Power

Configuration

346

422

486

PPR0 State 0 (REF0_x: 19.44 MHz, 3.3 V CMOS buffer; REF1_x: 19.44 MHz, 3.3 V

CMOS buffer)

PPR1 State 4 (PLL input ×2: off, OUT2: 155.52 MHz, HSTL; OUT3: 155.52 MHz, HSTL)

PPR2 State 4 (OUT0: disabled; OUT1: disabled)

PPR3 State 7 (OUT4: disabled; OUT5: disabled)

PPR4 State 0 (OUT6: disabled)

PPR5 State 0 (reference monitor threshold: not applicable (25 ppm)

PPR6 State 1 (MCLK_x: no connection (19.44 MHz, 3.3 V CMOS buffer))

REFMON: GND

Incremental Power

Dissipation

Typical configuration; values show the change in power due to the indicated

operation

Input Reference On/Off

Applies to one reference clock input

Single-Ended

0.23

0.30

0.36

Differential

20.5

25.1

30.0

Output Driver On/Off

LVDS (at 312.5 MHz)

18.1

22.5

27.2

HSTL (at 156.25 MHz)

30.6

36.6

42.5

1.8 V CMOS (at

66 MHz)

13.7

16.2

19.2

A single 1.8 V CMOS output with an 10 pF load

3.3 V CMOS (at

25 MHz)

9.5

12.2

15.2

A single 3.3 V CMOS output with an 10 pF load

Other Blocks On/Off

OUT0 ×2 On/Off

3.1

4.0

5.4

POWER SUPPLY CURRENT

(ISUPPLY)

Total supply current for VDD_x pins1 in aggregate

Typical Configuration

157

172

180

For power dissipation with typical configuration settings

All Blocks Running

Configuration

195

212

221

For power dissipation with all blocks running configuration settings

Minimal Power

Configuration

117

128

134

For power dissipation with minimal power configuration settings

1 VDD_x pins include VDD_REF0, VDD_REF1, VDD_OUT01, VDD_PLL, VDD_VCO, VDD_RFDIV, VDD_OUT6, VDD_OUT4, VDD_OUT5, VDD_OUT23, and VDD_MCLK.

TIMING SPECIFICATIONS

Typical is given for VS = 3.3 V ± 10%, TA = 25°C, unless otherwise noted. Minimum and maximum values are given over full VS and TA

(−40°C to +85°C) variation. The indicated times assume the voltage applied to all 3.3 V power supply pins is within specification and stable.

Table 16.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

MONITOR CLOCK INPUT

TO REF_FHI/REF_FLO TIME

Elapsed time from the first rising edge of the monitor clock input signal to

the valid reference status as indicated by the REF_FHI and REF_FLO pins (the

active reference must be stable)

fMCLK = 8 kHz

4200

fMCLK = 10 MHz

3400

fMCLK = 19.44 MHz

1800

fMCLK = 25 MHz

1400

fMCLK = 38.88 MHz

870

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