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INA1650 Datasheet(PDF) 21 Page - Texas Instruments |
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INA1650 Datasheet(HTML) 21 Page - Texas Instruments |
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21 / 38 page ![]() VMID(OUT) VMID(IN) VCC VEE 500 k 500 k CF RISO CLOAD REF A REF B Copyright © 2016, Texas Instruments Incorporated 50 55 60 65 70 75 80 85 90 95 10 100 1k 10k Frequency (Hz) F F / 1 M F F / 1 M C007 21 INA1650, INA1651 www.ti.com SBOS818A – DECEMBER 2016 – REVISED SEPTEMBER 2018 Product Folder Links: INA1650 INA1651 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Application Information (continued) Although the input resistors of the INA165x are matched typically within 0.01%, large capacitors are usually mismatched. The mismatch in the values of the AC-coupling capacitors causes the corner frequencies at the two signal inputs (IN+ and IN–) to be different, which can degrade CMRR at low frequency. For this reason, TI recommends placing the high-pass corner frequency well below the audio bandwidth and to use a resistor in series with the COM pin (RCOM), as shown in Figure 42 if possible. See the Common-Mode Input Impedance section for more information on placing a resistor in series with the COM pin. Figure 48 shows the effect of a 5% mismatch in the values of the input AC-coupling capacitors with and without an RCOM resistor. Comparing CMRR at 100 Hz: 1-µF AC-coupling capacitors with a 5% mismatch degrade the CMRR to 75 dB, while 10-µF capacitors and a 1-MΩ RCOM resistor shows 92 dB of CMRR. Figure 48. CMRR Degradation Due to a 5% Mismatch in AC-Coupling Capacitors 8.1.5 Supply Divider Capacitive Loading The VMID(OUT) pin of the INA165x is stable with capacitive loads up to 150 pF. An isolation resistor (RISO in Figure 49), must be used if capacitive loads larger than 150 pF are connected to the VMID(OUT) pin. Figure 49 shows the recommended configuration of an isolation resistor in series with the capacitive load. The REF pins of the INA1650 must connect directly to the VMID(OUT) pin before the isolation resistor. Any resistance placed between the VMID(OUT) pin and the reference pins degrades the CMRR of the device. Figure 50 shows the recommended value for the isolation resistor for increasing capacitive loads. Figure 49. Place an Isolation Resistor Between the VMID(OUT) Pin and Large Capacitive Loads |
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