Data Sheet

AD5316R

Rev. C | Page 7 of 24

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

12

11

10

1

3

4

A1

SCL

A0

2

GND

AD5316R

NOTES

1. THE EXPOSED PAD MUST BE TIED TO GND.

TOP VIEW

(Not to Scale)

Figure 3. 16-Lead LFCSP Pin Configuration

1

2

3

4

5

6

7

8

GND

SDA

16

15

14

13

12

11

10

9

RESET

A1

SCL

GAIN

LDAC

A0

RSTSEL

TOP VIEW

(Not to Scale)

AD5316R

Figure 4. 16-Lead TSSOP Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

Description

LFCSP

TSSOP

1

3

Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

2

4

GND

Ground Reference Point for All Circuitry on the Part.

3

5

Power Supply Input. The part can be operated from 2.7 V to 5.5 V. The supply should be decoupled

with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.

4

6

Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

5

7

Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

6

8

SDA

Serial Data Input. This pin is used in conjunction with the SCL line to clock data into or out of the

24-bit input shift register. SDA is a bidirectional, open-drain data line that should be pulled to the

supply with an external pull-up resistor.

7

9

LDAC

LDAC can be operated in two modes, asynchronous update mode and synchronous update mode.

Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new

data; all DAC outputs are simultaneously updated. This pin can also be tied permanently low.

8

10

GAIN

9

11

Digital Power Supply. Voltage ranges from 1.62 V to 5.5 V.

10

12

A0

Address Input. Sets the first LSB of the 7-bit slave address.

11

13

SCL

Serial Clock Line. This pin is used in conjunction with the SDA line to clock data into or out of the

24-bit input shift register.

12

14

A1

Address Input. Sets the second LSB of the 7-bit slave address.

13

15

RESET

Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is activated (low), the

input register and the DAC register are updated with zero scale or midscale, depending on the

state of the RSTSEL pin. When RESET is low, all LDAC pulses are ignored. If the pin is not used, tie it

until the pin is released.

14

16

RSTSEL

Power-On Reset Pin. When this pin is tied to GND, all four DACs are powered up to zero scale.

15

1

Reference Voltage. The AD5316R has an internal reference. When the internal reference is used,

pin. By default, the internal reference is used, and this pin is a reference output.

16

2

Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

17

N/A

EPAD

Exposed Pad. The exposed pad must be tied to GND.