AD5316R datasheet(17/24 Pages) AD

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Data Sheet

AD5316R

Rev. C | Page 17 of 24

SERIAL INTERFACE

The AD5316R has a 2-wire, I2C-compatible serial interface (see

the I2C-Bus Specification, Version 2.1, January 2000, available

from Philips Semiconductor). See Figure 2 for a timing diagram

of a typical write sequence. The AD5316R can be connected to

an I2C bus as a slave device, under the control of a master device.

The AD5316R supports standard (100 kHz) and fast (400 kHz)

data transfer modes. Support is not provided for 10-bit address-

ing or general call addressing.

Input Shift Register

The input shift register of the AD5316R is 24 bits wide. Data

is loaded into the device, MSB first, as a 24-bit word under the

control of the serial clock input, SCL. The input shift register

consists of an 8-bit command byte and a 16-bit data-word (see

Figure 41). The first eight MSBs make up the command byte.



The first four bits of the command byte are the command

bits (C3, C2, C1, and C0), which control the mode of

operation of the device (see Table 8).



The last four bits of the command byte are the address bits

(DAC D, DAC C, DAC B, and DAC A), which select the

DAC that is operated on by the command (see Table 9).

Table 8. Command Definitions

Command Bits

Command

No operation

Write to Input Register n (dependent

on LDAC)

Update DAC Register n with contents

of Input Register n

Write to and update DAC Channel n

Power down/power up DAC

Hardware LDAC mask register

Software reset (power-on reset)

Internal reference setup register

Reserved

1 X = don’t care.

Table 9. Address Bits and Selected DACs

Address Bits

Selected DAC Channels1

DAC D

DAC C

DAC B

DAC A

DAC B

DAC A and DAC B

DAC C

DAC A and DAC C

DAC B and DAC C

DAC A, DAC B, and DAC C

DAC D

DAC A and DAC D

…

All DACs

1 Any combination of DAC channels can be selected using the address bits.

The 8-bit command byte is followed by two data bytes, which con-

tain the data-word. The data-word comprises the 10-bit input code,

followed by six don’t care bits (see Figure 41). The data bits are

transferred to the input register on the 24 falling edges of SCL.

Commands can be executed on one DAC channel, any two or

three DAC channels, or on all four DAC channels, depending

on the address bits selected (see Table 9).

WRITE AND UPDATE COMMANDS

For more information about the LDAC function, see the Load

DAC (Hardware LDAC Pin) section.

Write to Input Register n (Dependent on LDAC)

Command 0001 allows the user to write to each DAC’s

dedicated input register individually. When LDAC is low, the

input register is transparent (if not controlled by the LDAC

mask register).

Update DAC Register n with Contents of Input Register n

Command 0010 loads the DAC registers/outputs with the

contents of the input registers selected by the address bits

(see Table 9) and updates the DAC outputs directly.

Write to and Update DAC Channel n (Independent of LDAC)

Command 0011 allows the user to write to the DAC registers

and update the DAC outputs directly, independent of the state

of the LDAC pin.

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

DAC D DAC C DAC B DAC A

COMMAND

DAC ADDRESS

DAC DATA

COMMAND BYTE

DATA HIGH BYTE

DATA LOW BYTE

Figure 41. Input Shift Register Contents

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