AD5316R datasheet(3/24 Pages) AD

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Data Sheet

AD5316R

Rev. C | Page 3 of 24

SPECIFICATIONS

VDD = 2.7 V to 5.5 V; VREF = 2.5 V; 1.62 V ≤ VLOGIC ≤ 5.5 V; RL = 2 kΩ; CL = 200 pF; all specifications TMIN to TMAX, unless otherwise noted.

Table 2.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments1, 2

STATIC PERFORMANCE3

Resolution

Bits

Relative Accuracy

±0.12

±0.5

LSB

Differential Nonlinearity

±0.5

LSB

Guaranteed monotonic by design

Zero-Code Error

0.4

1.5

All 0s loaded to DAC register

Offset Error

+0.1

±1.5

Full-Scale Error

+0.01

±0.1

% of FSR

All 1s loaded to DAC register

Gain Error

±0.02

±0.1

% of FSR

Total Unadjusted Error

±0.01

±0.1

% of FSR

External reference, gain = 2, TSSOP

±0.2

% of FSR

Internal reference, gain = 1, TSSOP

Offset Error Drift4

±1

µV/°C

Gain Temperature Coefficient4

±1

ppm

Of FSR/°C

DC Power Supply Rejection Ratio4

0.15

mV/V

DAC code = midscale; VDD = 5 V ± 10%

DC Crosstalk4

±2

µV

Due to single channel, full-scale output

change

±3

µV/mA

Due to load current change

±2

µV

Due to power-down (per channel)

OUTPUT CHARACTERISTICS4

Output Voltage Range

VREF

Gain = 1

2 × VREF

Gain = 2 (see Figure 25)

Capacitive Load Stability

RL = ∞

RL = 1 kΩ

Resistive Load5

kΩ

Load Regulation

DAC code = midscale

µV/mA

5 V ± 10%; −30 mA ≤ IOUT ≤ +30 mA

µV/mA

3 V ± 10%; −20 mA ≤ IOUT ≤ +20 mA

Short-Circuit Current6

Load Impedance at Rails7

Ω

See Figure 25

Power-Up Time

2.5

µs

Coming out of power-down mode; VDD = 5 V

REFERENCE OUTPUT

Output Voltage8

2.4975

2.5025

At TA

Reference TC9

ppm/°C

See the Terminology section

Output Impedance4

0.04

Ω

Output Voltage Noise4

µV p-p

0.1 Hz to 10 Hz

Output Voltage Noise Density4

240

nV/√Hz

At TA, f = 10 kHz, CL = 10 nF

Load Regulation, Sourcing4

µV/mA

At TA

Load Regulation, Sinking4

µV/mA

At TA

Output Current Load Capability4

±5

VDD ≥ 3 V

Line Regulation4

100

µV/V

At TA

Thermal Hysteresis4

125

ppm

First cycle

ppm

Additional cycles

LOGIC INPUTS4

Input Current

±2

µA

Per pin

Input Low Voltage, VINL

0.3 × VLOGIC

Input High Voltage, VINH

0.7 × VLOGIC

Pin Capacitance

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