Everest Semiconductor

ES7322

AIN4L/R

AIN3L/R

AIN2L/R

AIN1L/R

ES7322

+12 dB to –12 dB PGA

opam

5k

5k

5k

5k

5k

5k

5k

5k

5k

Figure 6 ADC Left and Right Inputs

The ADC has an analogue input PGA and digital gain control for each stereo

channel. The analog PGA has a range of +12 dB to –12 dB gains in 0.5 dB per

step. The digital gain control allows further attenuation (after the PGA) from

12.5 dB to 96 dB in 0.5 dB per step. ADC Left Gain Control register (RAM

address 0x04) and ADC Right Gain Control register (RAM address 0x05) allow

independent control of left and right channel gains.

Zero crossing detection and soft ramp control circuits are provided for the ADC

gain control (ADC Mute Control register, RAM address 0x03). This feature

minimizes the audible click and “zipper” noise as the gain values change.

11 DAC Fade In and Fade Out Transition

When DACMute bit in DAC Mute Control register (RAM address 0x08) is set,

the analog outputs go to mute level (common mode voltage) gradually at the

rate set by DACRampRate bits in the same register. Upon the release of the

DACMute bit, the analog outputs go up gradually at the same rate set by

DACRampRate bits. Please refer to Figure 7. The fade in and fade out feature

can be set or disabled by DACSoftRamp bit in the same register.

Mute Bit

Volume

Level

AOUT

The fade in and fade out feature is also available when AutoMute bit in DAC

Mute Control register (RAM address 0x08) is set to detect long stream of zero

input data.

Figure 7 Fade In/Out Diagram

Rev 3.0

April, 2006

15