ADP3168 datasheet(10/24 Pages) AD

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ADP3168

Rev. B | Page 10 of 24

The positive input of the CSA is connected to the CSREF pin,

which is connected to the output voltage. The inputs to the

amplifier are summed together through resistors from the

sensing element (such as the switch node side of the output

inductors) to the inverting input, CSSUM. The feedback resistor

between CSCOMP and CSSUM sets the gain of the amplifier,

and a filter capacitor is placed in parallel with this resistor.

The gain of the amplifier is programmable by adjusting the

feedback resistor to set the load line required by the micro-

processor. The current information is then given as the differ-

ence of CSREF − CSCOMP. This difference signal is used

internally to offset the VID DAC for voltage positioning and

as a differential input for the current-limit comparator.

To provide the best accuracy for the current sensing, the CSA

was designed to have a low offset input voltage. Also, the

sensing gain is determined by external resistors so that it can

be made extremely accurate.

ACTIVE IMPEDANCE CONTROL MODE

For controlling the dynamic output voltage droop as a function

of output current, a signal proportional to the total output

current at the CSCOMP pin can be scaled to be equal to the

droop impedance of the regulator times the output current.

This droop voltage is then used to set the input control voltage

to the system. The droop voltage is subtracted from the DAC

reference input voltage directly to tell the error amplifier where

the output voltage should be. This differs from previous

implementations and allows enhanced feed-forward response.

CURRENT-CONTROL MODE AND THERMAL

BALANCE

The ADP3168 has individual inputs that are used for

monitoring the current in each phase. This information is

combined with an internal ramp to create a current-balancing

feedback system that has been optimized for initial current

balance accuracy and dynamic thermal balancing during

operation. This current-balance information is independent of

the average output current information used for positioning

described previously.

The magnitude of the internal ramp can be set to optimize

the transient response of the system. It also monitors the

supply voltage for feed-forward control for changes in the

supply. A resistor connected from the power input voltage to

the RAMPADJ pin determines the slope of the internal PWM

ramp. Detailed information about programming the ramp is

given in the Application Information section.

External resistors can be placed in series with individual phases,

for example, to create an intentional current imbalance so one

phase may have better cooling and can support higher currents.

Resistors RSW1 through RSW4 (see the typical applica-tion circuit

in Figure 11) can be used for adjusting thermal balance. It is

best to add these resistors during the initial design, so make

sure placeholders are provided in the layout.

To increase the current in any given phase, make RSW for that

phase larger. (Make RSW = 0 for the hottest phase and do not

change during balancing.) Increasing RSW to only 500 Ω makes

a substantial increase in phase current. Increase each RSW value

by small amounts to achieve balance, starting with the coolest

phase first.

VOLTAGE CONTROL MODE

A high gain bandwidth voltage mode error amplifier is used for

the voltage-mode control loop. The control input voltage to the

positive input is set via the VID 6-bit logic code, according to

the voltages listed in Table 4. This voltage is also offset by the

droop voltage for active positioning of the output voltage as a

function of current, commonly known as active voltage

positioning. The output of the amplifier is the COMP pin,

which sets the termination voltage for the internal PWM ramps.

The negative input (FB) is tied to the output sense location with

a resistor, RB, and is used for sensing and controlling the output

voltage at this point. A current source from the FB pin flowing

through RB is used for setting the no-load offset voltage from

the VID voltage. The no-load voltage is negative with respect to

the VID DAC. The main loop compensation is incorporated

into the feedback network between FB and COMP.

SOFT START

The power-on ramp-up time of the output voltage is set with a

capacitor and a resistor in parallel from the DELAY pin to

ground. The RC time constant also determines the current-limit

latch-off time, as explained in the following section. In UVLO

or when EN is a logic low, the DELAY pin is held at ground.

After the UVLO threshold is reached and EN is a logic high, the

DELAY capacitor is charged up with an internal 20 µA current

source. The output voltage follows the ramping voltage on the

DELAY pin, limiting the inrush current. The soft-start time

depends on the values of VID DAC and CDLY, with a secondary

effect from RDLY. Refer to the Application Information section

for detailed information on setting CDLY.

When the PWRGD threshold is reached, the soft-start cycle is

stopped and the DELAY pin is pulled up to 3 V. This ensures

that the output voltage is at the VID voltage when the PWRGD

signals to the system that the output voltage is good. If EN is

taken low or VCC drops below UVLO, the DELAY capacitor is

reset to ground to be ready for another soft-start cycle. Figure 8

shows a typical start-up sequence for the ADP3168.

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