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ADP3168 Datasheet(PDF) 17 Page - Analog Devices |
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ADP3168 Datasheet(HTML) 17 Page - Analog Devices |
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17 / 24 page  ADP3168 Rev. B | Page 17 of 24 COUT SELECTION The required output decoupling for the regulator is typically recommended by Intel for various processors and platforms. One can also use some simple design guidelines to determine what is required. These guidelines are based on having both bulk and ceramic capacitors in the system. The first thing is to select the total amount of ceramic capaci- tance. This is based on the number and type of capacitor to be used. The best location for ceramics is inside the socket, with 12 to 18 of size 1206 being the physical limit. Others can be placed along the outer edge of the socket as well. Combined ceramic values of 200 µF to 300 µF are recom- mended, usually made up of multiple 10 µF or 22 µF capacitors. Select the number of ceramics and then find the total ceramic capacitance (CZ). Next, there is an upper limit imposed on the total amount of bulk capacitance (CX) when one considers the VID on-the-fly voltage stepping of the output (voltage step VV in time tV with error of VERR) and a lower limit based on meeting the critical capacitance for load release for a given maximum load step ∆IO: () ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ − × × × ≥ z VID O O MIN x C V R n I L C Δ (12) () ≤ MAX x C z O V VID v VID V O C L nKR V V t V V R nK L − ⎟ ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎜ ⎝ ⎛ − ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ × + × × 1 1 2 2 2 (13) ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ = V ERR V V n K 1 where To meet the conditions of these expressions and transient re- sponse, the ESR of the bulk capacitor bank (RX) should be less than two times the droop resistance, RO. If the CX(MIN) is larger than CX(MAX), the system does not meet the VID on-the-fly specification and may require the use of a smaller inductor or more phases (and may have to increase the switching frequency to keep the output ripple the same). For our example, 23 10 µF 1206 MLC capacitors (CZ = 230 µF) were used. The VID on-the-fly step change is 250 mV in 150 µs with a setting error of 2.5 mV. Solving for the bulk capacitance yields () mF 92 . 5 µF 230 V 5 . 1 Ω m 3 . 1 3 A 60 nH 600 = ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ − × × × ≤ MIN x C () () × × × × × ≤ V 5 . 1 Ω m 3 . 1 6 . 4 3 mV 250 nH 600 2 2 MAX x C mF 9 . 23 µF 230 1 nH 600 mV 250 Ω m 3 . 1 6 . 4 3 V 5 . 1 µs 150 1 2 = − ⎟ ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎜ ⎝ ⎛ − ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ × × × × × + where k = 4.6 Using eight 820 µF A1-Polys with a typical ESR of 8 mΩ each yields CX = 6.56 mF with an RX = 1.0 mΩ. One last check should be made to ensure that the ESL of the bulk capacitors (LX) is low enough to limit the initial high frequency transient spike. This is tested using () pH 389 Ω m 3 . 1 µF 230 2 = × ≤ × ≤ x z x L R C L (14) In this example, LX is 375 pH for the eight A1-Polys capacitors, which satisfies this limitation. If the LX of the chosen bulk capacitor bank is too large, the number of capacitors must be increased. One should note that for this multimode control technique, all ceramic designs can be used as long as the conditions of Equations 11, 12, and 13 are satisfied. |
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