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ADP3168

Rev. B | Page 18 of 24

POWER MOSFETS

For this example, the N-channel power MOSFETs have been

selected for one high-side switch and two low-side switches per

phase. The main selection parameters for the power MOSFETs

are VGS(TH), QG, CISS, CRSS, and RDS(ON). The minimum gate drive

voltage (the supply voltage to the ADP3418) dictates whether

standard threshold or logic-level threshold MOSFETs must be

used. With VGATE ~10 V, logic-level threshold MOSFETs (VGS(TH)

<2.5 V) are recommended.

The maximum output current IO determines the RDS(ON) require-

ment for the low-side (synchronous) MOSFETs. The ADP3168,

balances currents between phases, thus the current in each low-

side MOSFET is the output current divided by the total number

of MOSFETs (nSF). With conduction losses being dominant, the

following expression shows the total power being dissipated in

each synchronous MOSFET in terms of the ripple current per

phase (IR) and average total output current (IO):

()

( )

⎥

⎦

⎤

⎢

⎣

⎡

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

−

(15)

Knowing the maximum output current being designed for and

the maximum allowed power dissipation, one can find the

required RDS(ON) for the MOSFET. For D-PAK MOSFETs up to

an ambient temperature of 50°C, a safe limit for PSF is 1 W to

1.5 W at 120°C junction temperature. Thus, for this example

(65 A maximum), we find RDS(SF) (per MOSFET) < 8.7 mΩ.

This RDS(SF) is also at a junction temperature of about 120°C,

so we need to make sure we account for this when making

this selection. For this example, we selected two lower-side

MOSFETs at 7 mΩ each at room temperature, which gives

8.4 mΩ at high temperature.

Another important factor for the synchronous MOSFET is

the input capacitance and feedback capacitance. The ratio

of the feedback to input needs to be small (less than 10%

is recommended) to prevent accidental turn-on of the

synchronous MOSFETs when the switch node goes high.

Also, the time to switch the synchronous MOSFETs off should

not exceed the nonoverlap dead time of the MOSFET driver

(40 ns typical for the ADP3418). The output impedance of

the driver is about 2 Ω and the typical MOSFET input gate

resistances are about 1 Ω to 2 Ω, so a total gate capacitance of

less than 6000 pF should be adhered to. Because there are

two MOSFETs in parallel, the input capacitance for each

synchronous MOSFET should be limited to 3000 pF.

The high-side (main) MOSFET must be able to handle two

main power dissipation components: conduction and switching

losses. The switching loss relates to the amount of time it takes

for the main MOSFET to turn on and off, and to the current

and voltage that are being switched. Basing the switching speed

on the rise and fall time of the gate driver impedance and

MOSFET input capacitance, the following expression provides

an approximate value for the switching loss per main MOSFET,

where nMF is the total number of main MOSFETs:

()

ISS

= 2

(16)

Here, RG is the total gate resistance (2 Ω for the ADP3418 and

about 1 Ω for typical high speed switching MOSFETs, making

RG = 3 Ω) and CISS is the input capacitance of the main

MOSFET. Note that adding more main MOSFETs (nMF) does

not really help the switching loss per MOSFET because the

additional gate capacitance slows switching. The best thing to

reduce switching loss is to use lower gate capacitance devices.

The conduction loss of the main MOSFET is given by the

following, where RDS(MF) is the ON resistance of the MOSFET:

()

(

)

⎥

⎦

⎤

⎢

⎣

⎡

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛ ×

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

(17)

Typically, for main MOSFETs, the highest speed (low CISS)

device is preferred, but these usually have higher ON resistance.

Select a device that meets the total power dissipation (about

1.5 W for a single D-PAK) when combining the switching and

conduction losses.

For this example, an Infineon IPD12N03L was selected as the

main MOSFET (three total; nMF = 3), with a CISS = 1460 pF

(max) and RDS(MF) = 14 mΩ (max at TJ = 120°C), and an

Infineon IPD06N03L was selected as the synchronous

MOSFET (six total; nSF = 6), with CISS = 2370 pF (max) and

RDS(SF) = 8.4 mΩ (max at TJ = 120°C). The synchronous

MOSFET CISS is less than 3000 pF, satisfying that requirement.

Solving for the power dissipation per MOSFET at IO = 65 A and

IR = 8.2 A yields 863 mW for each synchronous MOSFET and

1.44 W for each main MOSFET. These numbers work well

considering there is usually more PCB area available for each

main MOSFET vs. each synchronous MOSFET.

One last thing to consider is the power dissipation in the driver

for each phase. This is best described in terms of the QG for the

MOSFETs and is given by the following, where QGMF is the total

gate charge for each main MOSFET and QGSF is the total gate

charge for each synchronous MOSFET:

()

GSF

GMF

DRV

⎥

⎦

⎤

⎢

⎣

⎡

(18)

Also shown is the standby dissipation factor (ICC × VCC) for

the driver. For the ADP3418, the maximum dissipation should

be less than 400 mW. For our example, with ICC = 7 mA,

QGMF = 22.8 nC, and QGSF = 34.3 nC, we find 260 mW in each

driver, which is below the 400 mW dissipation limit. See the

ADP3418 data sheet for more details.

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