ADP3168 datasheet(19/24 Pages) AD

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ADP3168

Rev. B | Page 19 of 24

RAMP RESISTOR SELECTION

The ramp resistor (RR) is used for setting the size of the internal

PWM ramp. The value of this resistor is chosen to provide the

best combination of thermal balance, stability, and transient

response. This expression determines the optimum value:

Ω

381

Ω

600

(19)

where AR is the internal ramp amplifier gain, AD is the current

balancing amplifier gain, RDS is the total low-side MOSFET ON

resistance, and CR is the internal ramp capacitor value. The

closest standard 1% resistor value is 383 kΩ.

The internal ramp voltage magnitude can be calculated using

()

kHz

267

Ω

383

125

−

VID

(20)

The size of the internal ramp can be made larger or smaller. If

it is made larger, stability and transient response improve, but

thermal balance degrades. Likewise, if the ramp is made

smaller, thermal balance improves at the sacrifice of transient

response and stability. The factor of three in the denominator of

Equation 19 sets a ramp size that gives an optimal balance for

good stability, transient response, and thermal balance.

COMP PIN RAMP

There is a ramp signal on the COMP pin due to the droop

voltage and output voltage ramps. This ramp amplitude adds to

the internal ramp to produce the following overall ramp signal

at the PWM input.

(

)

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

−

(21)

For this example, the overall ramp signal is found to be 0.63 V.

CURRENT-LIMIT SET POINT

To select the current-limit set point, first find the resistor value

for RLIM. The current limit threshold for the ADP3168 is set

with a 3 V source (VLIM) across RLIM with a gain of 10.4 mV/µA

(ALIM). RLIM can be found using the following:

LIM

(22)

For values of RLIM greater than 500 kΩ, the current limit may

be lower than expected, so some adjustment of RLIM may be

needed. Here, ILIM is the average current limit for the output of

the supply. For our example, choosing 120 A for ILIM, we find

RLIM to be 200 kΩ, for which we chose 200 kΩ as the nearest

1% value.

The per-phase current limit described earlier has its limit

determined by the following:

()

MAX

BIAS

MAX

COMP

PHLIM

−

≅

(23)

For the ADP3168, the maximum COMP voltage (VCOMP(MAX)) is

3.3 V, the COMP pin bias voltage (VBIAS) is 1.2 V, and the

current balancing amplifier gain (AD) is 5. Using VR of 0.63 V

and RDS(MAX) of 4.2 mΩ (low-side ON resistance at 150°C), we

find a per-phase limit of 66 A.

This limit can be adjusted by changing the ramp voltage VR, but

make sure not to set the per-phase limit lower than the average

per-phase current (ILIM/n).

There is also a per-phase initial duty cycle limit determined by

()

BIAS

MAX

COMP

MAX

−

(24)

For this example, the maximum duty cycle is found to be 0.42.

FEEDBACK LOOP COMPENSATION DESIGN

Optimized compensation of the ADP3168 allows the best

possible response of the regulator’s output to a load change. The

basis for determining the optimum compensation is to make

the regulator and output decoupling appear as an output

impedance that is entirely resistive over the widest possible

frequency range, including dc, and equal to the droop resistance

(RO). With the resistive output impedance, the output voltage

droops in proportion with the load current at any load current

slew rate; this ensures the optimal positioning and allows the

minimization of the output decoupling.

With the multimode feedback structure of the ADP3168, the

feedback compensation must be set to make the converter’s

output impedance, working in parallel with the output

decoupling, meet this goal. There are several poles and zeros

created by the output inductor and decoupling capacitors

(output filter) that need to be compensated for.

A type-three compensator on the voltage feedback is adequate

for proper compensation of the output filter. The expressions

given in Equations 25 to 29 are intended to yield an optimal

starting point for the design; some adjustments may be

necessary to account for PCB and component parasitic effects

(see the Tuning Procedure for the ADP3168).

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