ADP3168 datasheet(22/24 Pages) AD

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ADP3168

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AC Loadline Setting

11. Remove dc load from circuit and hook up dynamic load.

12. Hook up scope to output voltage and set to dc coupling

with time scale at 100 µs/div.

13. Set dynamic load for a transient step of about 40 A at 1

kHz with 50% duty cycle.

14. Measure output waveform (may have to use dc offset on

scope to see waveform). Try to use vertical scale of 100

mV/div or finer.

15. This waveform should look something like Figure 15. Use

the horizontal cursors to measure VACDRP and VDCDRP as

shown. Do not measure the undershoot or overshoot that

happens immediately after the step.

VACDRP

VDCDRP

Figure 15. AC Loadline Waveform

16. If the VACDRP and VDCDRP are different by more than a few

millivolts, use Equation 38 to adjust CCS. Parallel different

values to get the right one because there are limited

standard capacitor values available. (Make sure that there

are locations for two capacitors in the layout for this.)

()

DCDRP

ACDRP

OLD

NEW

(38)

17. Repeat Steps 11 to 13, making adjustments if necessary.

Once complete, do not change CCS again in the procedure.

18. Set dynamic load step to maximum step size (do not use a

step size larger than needed) and verify that the output

waveform is square (which means VACDRP and VDCDRP are

equal).Make sure load step slew rate and turn-on are set for

a slew rate of ~150 A/µs to 250 A/µs (for example, a load

step of 50 A should take 200 ns to 300 ns) with no overshoot.

Some dynamic loads have an excessive turn-on overshoot if

a minimum current is not set properly. (This is an issue if

using a VTT tool.)

Initial Transient Setting

19. With dynamic load still set at maximum step size, expand

scope time scale to see 2 µs/div to 5 µs/div. The waveform

may have two overshoots and one minor undershoot (see

Figure 16). Here, VDROOP is the final desired value.

VDROOP

VTRAN1

VTRAN2

Figure 16. Transient Setting Waveform

20. If both overshoots are larger than desired, try making the

adjustments described below. (Note: If these adjustments

do not change the response, you are limited by the output

decoupling.) Check the output response each time you

make a change as well as the switching nodes (to make sure

the response is still stable).

Make ramp resistor larger by 25% (RRAMP).

For VTRAN1, increase CB or increase switching

frequency.

For VTRAN2, increase RA and decrease CA by 25%.

21. For load release (see Figure 17), if VTRANREL is larger than

VTRAN1 (see Figure 16), there is not enough output

capacitance. You will either need more capacitance or have

to make the inductor values smaller. (If you change

inductors, you will need to start the design over using the

spreadsheet and this tuning procedure.)

VDROOP

VTRANREL

Figure 17. Transient Setting Waveform

Because the ADP3168 turns off all of the phases (switches

inductors to ground), there is no ripple voltage present during

load release. Thus, you do not have to add headroom for ripple,

allowing your load release VTRANREL to be larger than VTRAN1 by

the amount of ripple and still meet specifications.

If VTRAN1 and VTRANREL are less than the desired final droop, this

implies that capacitors can be removed. When removing

capacitors, check the output ripple voltage as well to make sure

it is still within specifications.

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