ADV7183ABST datasheet(32/104 Pages) AD

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ADV7183A

Rev. A | Page 32 of 104

CSFM[2:0] C Shaping Filter Mode (SDP), Address 0x17, [7]

The C shaping filter mode bits allow the user to select from a

range of low-pass filters for the chrominance signal. When

switched in automatic mode, the widest filter is selected based

on the video standard/format and user choice (see settings 000

and 001 in Table 63).

Table 63. CSFM Function

CSFM[2:0]

Description

000*

Autoselect 1.5 MHz bandwidth

001

Autoselect 2.17 MHz bandwidth

010

SH1

011

SH2

100

SH3

101

SH4

110

SH5

111

Wideband Mode

*Default value.

–10

–20

–30

–40

–50

–60

FREQUENCY (MHz)

v740a COMBINED C ANTIALIAS, C SHAPING FILTER,

C RESAMPLER

Figure 16. SDP Chroma Shaping Filter Responses

Figure 16 shows the responses of SH1 (narrowest) to SH5

(widest) in addition to the wideband mode (in red).

SDP GAIN OPERATION

The gain control within the ADV7183A is done on a purely

digital basis. The input ADCs support a 10-bit range, mapped

into a 1.6 V analog voltage range. Gain correction takes place

after the digitization in the form of a digital multiplier.

There are several advantages of this architecture over the

commonly used PGA (programmable gain amplifier) before the

ADCs; among them is the fact that the gain is now completely

independent of supply, temperature, and process variations.

As shown in Figure 17, the ADV7183A can decode a video

signal as long as it fits into the ADC window. There are two

components to this: the amplitude of the input signal and the dc

level it resides on. The dc level is set by the clamping circuitry

(see the SDP Clamp Operation section).

If the amplitude of the analog video signal is too high, clipping

may occur, resulting in visual artifacts. The analog input range

of the ADC, together with the clamp level, determines the

maximum supported amplitude of the video signal.

The minimum supported amplitude of the input video is

determined by the SDP core’s ability to retrieve horizontal and

vertical timing and to lock to the color burst (if present).

There are two gain control units, one each for luma and chroma

data. Both can operate independently of each other. The chroma

unit, however, can also take its gain value from the luma path.

Several AGC modes are possible; Table 64 summarizes them.

It is possible to freeze the automatic gain control loops. This will

cause the loops to stop updating and the AGC determined gain

at the time of the freeze stays active until the loop is either

unfrozen or the gain mode of operation is changed.

The currently active gain from any of the modes can be read

back. Please refer to the description of the dual function manual

gain registers, LG[11:0] Luma Gain and CG[11:0] Chroma

Gain, in the SDP Luma Gain and SDP Chroma Gain sections.

ANALOG VOLTAGE

RANGE SUPPORTED BY ADC (1.6V RANGE FOR ADV7183A)

DATA

PRE

PROCESSOR

(DPP)

ADC

SDP

(GAIN SELECTION ONLY)

MAXIMUM

VOLTAGE

MINIMUM

VOLTAGE

CLAMP

LEVEL

GAIN

CONTROL

Figure 17. SDP Gain Control Overview

ADV7183ABST Datasheet(PDF) 32 Page - Analog Devices

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