ADV7183ABST datasheet(64/104 Pages) AD

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ADV7183A

Rev. A | Page 64 of 104

MPU PORT DESCRIPTION

The ADV7183A supports a 2-wire (I2C compatible) serial inter-

face. Four inputs, serial data (SDA1 and SDA2) and serial clock

(SCLK1 and SCLK2), carry information between the

ADV7183A and the system I2C master controller. Each slave

device is recognized by a unique address. The ADV7183A has

two ports: the control port, which allows the user to set up and

configure the decoder; and the VBI data readback port, which

allows the user to read back captured VBI data. Both the control

and VBI ports have four possible slave addresses for both read

and write operations, depending on the logic level on the ALSB

pin. These four unique addresses are shown in Table 170. The

ADV7183A’s ALSB pin controls Bit 1 of the slave address. By

altering the ALSB, it is possible to control two ADV7183As in

an application without having a conflict with the same slave

address. The LSB (Bit 0) sets either a read or write operation.

Logic 1 corresponds to a read operation; Logic 0 corresponds to

a write operation.

Table 170. I2C Address for ADV7183A

ALSB

R/W

Slave Address

Control Port

Slave Address

VBI Port

0x40

0x20

0x41

0x21

0x42

0x22

0x43

0x23

To control the device on the bus, a specific protocol must be

followed. First, the master initiates a data transfer by establish-

ing a Start condition, which is defined by a high-to-low

transition on SDA1/SDA2 while SCLK1/SCLK2 remains high.

This indicates that an address/data stream will follow. All per-

ipherals respond to the Start condition and shift the next eight

bits (7-bit address + R/W bit). The bits are transferred from

MSB down to LSB. The peripheral that recognizes the trans-

mitted address responds by pulling the data line low during the

ninth clock pulse; this is known as an acknowledge bit. All other

devices withdraw from the bus at this point and maintain an

idle condition. The idle condition is where the device monitors

the SDA1/SDA2 and SCLK1/SCLK2 lines, waiting for the Start

condition and the correct transmitted address. The R/W bit

determines the direction of the data. Logic 0 on the LSB of the

first byte means the master will write information to the

peripheral. Logic 1 on the LSB of the first byte means the master

will read information from the peripheral.

The ADV7183A acts as a standard slave device on the bus. The

data on the SDA pin is eight bits long, supporting the 7-bit

addresses plus the R/W bit. The ADV7183A has 196 subad-

dresses to enable access to the internal registers. It therefore

interprets the first byte as the device address and the second

byte as the starting subaddress. The subaddresses auto-

increment, allowing data to be written to or read from the

starting subaddress. A data transfer is always terminated by a

Stop condition. The user can also access any unique subaddress

Stop and Start conditions can be detected at any stage during

the data transfer. If these conditions are asserted out of

sequence with normal read and write operations, they cause an

immediate jump to the idle condition. During a given SCLK

high period, the user should only issue one Start condition, one

Stop condition, or a single Stop condition followed by a single

Start condition. If an invalid subaddress is issued by the user,

the ADV7183A will not issue an acknowledge and will return to

the idle condition.

If in auto-increment mode the user exceeds the highest

subaddress, the following action is taken:

In read mode, the highest subaddress register contents

continue to be output until the master device issues a no-

acknowledge. This indicates the end of a read. A no-

acknowledge condition is where the SDA line is not pulled

low on the ninth pulse.

In write mode, the data for the invalid byte is not loaded

into any subaddress register, a no acknowledge is issued by

the ADV7183A, and the part returns to the idle condition.

SDATA

SCLOCK

START ADDR

ACK

DATA

ACK

STOP

SUBADDRESS

1–7

R/W

Figure 36. Bus Data Transfer

WRITE

SEQUENCE

SLAVE ADDR

A(S)

SUB ADDR

A(S)

DATA

A(S)

DATA

A(S)

READ

SEQUENCE

SLAVE ADDR

A(S)

SUB ADDR

A(S) S

A(S)

DATA

A(M)

DATA

A(M) P

S = START BIT

P = STOP BIT

A(S) = ACKNOWLEDGE BY SLAVE

A(M) = ACKNOWLEDGE BY MASTER

A(S) = NO-ACKNOWLEDGE BY SLAVE

A(M) = NO-ACKNOWLEDGE BY MASTER

LSB = 1

LSB = 0

Figure 37: Read and Write Sequence

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